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11. 发明申请

US20080127187A1 TRACE BUFFER WITH A PROCESSOR 有权
标题翻译：跟加工商的缓冲区
公开(公告)号：US20080127187A1
公开(公告)日：2008-05-29
申请号：US11530051
申请日：2006-09-08
申请人： Kun Xu , Jen-Tien Yen
发明人： Kun Xu , Jen-Tien Yen
IPC分类号： G06F9/46
CPC分类号： G06F11/3476 , G06F11/3466 , G06F2201/87
摘要： A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
摘要翻译：一种方法包括将第一交易条目存储到第一软件可配置存储位置，将第二交易条目存储到第二软件可配置存储位置，确定由第一交易条目指示的第一交易已经发生，确定由第一交易条目指示的第二交易第二交易条目已经在第一交易之后发生，并且响应于确定第一交易发生和第二交易发生，存储在第二交易之后的至少一个时钟周期期间捕获的至少一个交易属性。第一和第二软件可配置存储位置可以位于跟踪缓冲器中，其中至少一个事务属性被存储到跟踪缓冲器并且覆盖第一和第二事务属性。每个交易条目可以包括死循环字段，连续交易需求字段和最后输入字段。

12. 发明授权

US06240490B1 Comprehensive multilevel cache preloading mechanism in a multiprocessing simulation environment 失效
标题翻译：多处理仿真环境中的综合多级缓存预加载机制
公开(公告)号：US06240490B1
公开(公告)日：2001-05-29
申请号：US09119310
申请日：1998-07-20
申请人： Joseph William Lyles, Jr. , Jen-Tien Yen , Qichao Yin , Mark David Griswold
发明人： Joseph William Lyles, Jr. , Jen-Tien Yen , Qichao Yin , Mark David Griswold
IPC分类号： G06F1200
CPC分类号： G06F12/0811
摘要： For simulation of a multiprocessor system having a multi-level cache hierarchy, possible and legal cache coherency state combinations are classified based on the state of one level one cache, and subclassified within the major classes to define unique combinations, a number significantly less than the number of all possible combinations. For data words in the test case, a cache coherency state combination is randomly selected from a combination table listing all subclasses. Stale data generated by inverting all or part of the original data from the test case may be preloaded with the coherency states as necessary. Existing coherency is maintained when test case data is preloaded to a cache location already preloaded to avoid previously loaded stale data from becoming valid with the new coherency state. Coherency state combinations which are preloaded are tracked to help ensure that all subclasses an are preloaded and tested during simulation prior to tapeout. The cache preload mechanism of the present invention allows bugs which only occur when the caches are in some corner case states to be detected.
摘要翻译：为了模拟具有多级高速缓存层级的多处理器系统，可能和合法的高速缓存一致性状态组合基于一级缓存的状态分类，并且在主类中被分类以定义唯一的组合，数量明显小于所有可能组合的数量。对于测试用例中的数据字，从列出所有子类的组合表中随机选择高速缓存一致性状态组合。通过将来自测试用例的全部或部分原始数据反转而产生的陈旧数据可能需要预先加载一致性状态。当测试用例数据被预加载到已经预加载的高速缓存位置时，保持现有的一致性，以避免先前加载的过期数据在新的一致性状态下变得有效。跟踪预先加载的一致性状态组合，以帮助确保在进行流片化之前，模拟期间预先加载和测试所有子类。本发明的高速缓存预加载机制允许仅在高速缓存处于某些角度状态时被检测到的错误。

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