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11. 发明授权

US08059483B2 Address receiving circuit for a semiconductor apparatus 有权
标题翻译：半导体装置的地址接收电路
公开(公告)号：US08059483B2
公开(公告)日：2011-11-15
申请号：US12834429
申请日：2010-07-12
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.
摘要翻译：一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及地址缓冲器，根据控制信号接收地址。

12. 发明申请

US20100278004A1 ADDRESS RECEIVING CIRCUIT FOR A SEMICONDUCTOR APPARATUS 有权
标题翻译：地址接收电路用于半导体器件
公开(公告)号：US20100278004A1
公开(公告)日：2010-11-04
申请号：US12834429
申请日：2010-07-12
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/06
CPC分类号： G11C8/06
摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.
摘要翻译：一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及地址缓冲器，根据控制信号接收地址。

13. 发明申请

US20090168565A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20090168565A1
公开(公告)日：2009-07-02
申请号：US12164984
申请日：2008-06-30
申请人： Kyoung-Nam KIM , Ho-Youb Cho
发明人： Kyoung-Nam KIM , Ho-Youb Cho
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C7/222 , G11C29/022 , G11C29/023
摘要： Semiconductor memory device and method for operating the same comprise an auxiliary driver configured to output an internal strobe signals generated corresponding to a read command as a plurality of auxiliary strobe signal in response to a control signal, wherein the auxiliary driver bypass a first output auxiliary strobe signal, and delay to output the rest of the auxiliary strobe signal among the outputted auxiliary strobe signal and a strobe signal generator for driving the auxiliary strobe signal to output the delayed auxiliary strobe signal as a data strobe signals.
摘要翻译：半导体存储器件及其操作方法包括：辅助驱动器，被配置为响应于控制信号输出与读命令相对应的内部选通信号作为多个辅助选通信号，其中辅助驱动器绕过第一输出辅助选通信号和延迟以输出辅助选通信号中的其余的辅助选通信号和选通信号发生器，用于驱动辅助选通信号以输出延迟的辅助选通信号作为数据选通信号。

14. 发明授权

US07532527B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07532527B2
公开(公告)日：2009-05-12
申请号：US11528519
申请日：2006-09-28
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C7/1048 , G11C7/1066
摘要： A semiconductor memory device includes a bank including a plurality of cell blocks; a first group of local input/output lines to transfer data stored on a first group of the cell blocks; a second group of local input/output lines to transfer data stored on a second group of the cell blocks; a first precharge unit precharging the first group of the local input/output lines; a second precharge unit precharging the second group of the local input/output lines; a precharge signal generator to precharge the first and second groups of the cell blocks and the second group of the cell blocks.
摘要翻译：一种半导体存储器件包括：一个包括多个单元块的单元; 用于传送存储在第一组单元块上的数据的第一组本地输入/输出线; 第二组本地输入/输出线，用于传送存储在第二组单元块上的数据; 第一预充电单元对所述第一组本地输入/输出线预充电; 第二预充电单元对所述第二组本地输入/输出线进行预充电; 预充电信号发生器，用于对第一和第二组单元块和第二组单元块进行预充电。

15. 发明授权

US07515482B2 Pipe latch device of semiconductor memory device 有权
标题翻译：半导体存储器件的锁闩装置
公开(公告)号：US07515482B2
公开(公告)日：2009-04-07
申请号：US11477384
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C19/28 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.
摘要翻译：管闩锁装置包括：输出控制器，用于基于DLL时钟信号和驱动信号输出第一和第二输出控制信号组; 用于产生输入控制信号组的输入控制器; 以及管锁存单元，用于当相应的输入控制信号被激活时将数据锁存在数据线上，并且当相应的输出控制信号被激活时输出锁存的数据，其中输出控制器包括多个移位器，每个移位器用于延迟输入数据信号通过半时钟和一个时钟与DLL时钟信号和驱动信号同步地输出第一和第二输出信号; 以及多个输出控制信号驱动器，用于基于第一和第二输出信号输出第一和第二输出控制信号组。

16. 发明授权

US07349290B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07349290B2
公开(公告)日：2008-03-25
申请号：US11323687
申请日：2005-12-30
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C2207/105
摘要： A semiconductor memory device is provided. The semiconductor memory device includes: a first input/output control unit for changing a sensing node into a first level in response to an activation of a first enabling signal for enabling an output of a data synchronized with a rising edge of a clock signal; a second input/output control unit for changing the sensing node into a second level in response to a delay locked clock signal as the second input/output control unit is enabled when the first enabling signal and a second enabling signal for enabling an output of a data synchronized with a falling edge of the clock signal are disabled; an output unit for outputting an input/output control signal; and a data output driver for outputting a data as the data output driver is activated in response to a first level of the input/output control signal.
摘要翻译：提供半导体存储器件。半导体存储器件包括：第一输入/输出控制单元，用于响应于激活与第一时钟信号的上升沿同步的数据的第一使能信号的激活，将感测节点改变为第一电平; 第二输入/输出控制单元，用于响应于延迟锁定时钟信号而将感测节点改变为第二电平，因为当第一使能信号和第二使能信号用于使能输出信号时，第二输入/输出控制单元被使能与时钟信号下降沿同步的数据被禁止; 用于输出输入/输出控制信号的输出单元; 并且响应于输入/输出控制信号的第一电平激活用于输出作为数据输出驱动器的数据的数据输出驱动器。

17. 发明申请

US20070076501A1 Semiconductor memory device and driving method thereof 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20070076501A1
公开(公告)日：2007-04-05
申请号：US11529570
申请日：2006-09-29
申请人： Sang-Hee Kang , Hi-Hyun Han , Ho-Youb Cho
发明人： Sang-Hee Kang , Hi-Hyun Han , Ho-Youb Cho
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C7/02 , G11C7/065 , G11C11/4091 , G11C2207/065
摘要： A semiconductor memory device prevents deterioration of refresh operation caused by sensing noise and a driving method thereof. First pull-down and second pull-down voltages which are different from each other are as a pull-down voltage of a bit line sense amplifier. The first and the second pull-down voltages are used in different driving periods to protect data from noises caused by another memory bank. A driving period can be separated into an initial sensing period, wherein large currents are consumed and significant noise is generated, and a subsequent stable period. The driving period can be separated into a pre-precharge period and a post-precharge period.
摘要翻译：半导体存储器件防止由感测噪声引起的刷新操作的劣化及其驱动方法。彼此不同的第一下拉和第二下拉电压作为位线读出放大器的下拉电压。第一和第二下拉电压用于不同的驱动周期以保护数据免受另一个存储体引起的噪声。驱动周期可以分为初始感测周期，其中消耗大电流并产生显着的噪声，以及随后的稳定周期。驱动周期可以分为预充电期和预充电期。

18. 发明申请

US20070070670A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070070670A1
公开(公告)日：2007-03-29
申请号：US11528519
申请日：2006-09-28
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C5/02
CPC分类号： G11C7/1045 , G11C7/1048 , G11C7/1066
摘要： A semiconductor memory device includes a bank including a plurality of cell blocks; a first group of local input/output lines to transfer data stored on a first group of the cell blocks according to a first data output mode; a second group of local input/output lines to transfer data stored on a second group of the cell blocks according to the first data output mode and a second data output mode; a first precharge unit precharging the first group of the local input/output lines; a second precharge unit precharging the second group of the local input/output lines; a precharge signal generator to precharge the first and second groups of the cell blocks for the first data output mode and the second group of the cell blocks for the second data output mode.
摘要翻译：一种半导体存储器件包括：一个包括多个单元块的单元; 第一组本地输入/输出线，用于根据第一数据输出模式传送存储在第一组单元块上的数据; 第二组本地输入/输出线，用于根据第一数据输出模式和第二数据输出模式传送存储在第二组单元块上的数据; 第一预充电单元对所述第一组本地输入/输出线预充电; 第二预充电单元对所述第二组本地输入/输出线进行预充电; 预充电信号发生器，用于对第一数据输出模式的第一和第二组单元块进行预充电，以及用于第二数据输出模式的第二组单元块。

19. 发明申请

US20060280025A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060280025A1
公开(公告)日：2006-12-14
申请号：US11323687
申请日：2005-12-30
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C2207/105
摘要： A semiconductor memory device is provided. The semiconductor memory device includes: a first input/output control unit for changing a sensing node into a first level in response to an activation of a first enabling signal for enabling an output of a data synchronized with a rising edge of a clock signal; a second input/output control unit for changing the sensing node into a second level in response to a delay locked clock signal as the second input/output control unit is enabled when the first enabling signal and a second enabling signal for enabling an output of a data synchronized with a falling edge of the clock signal are disabled; an output unit for outputting an input/output control signal; and a data output driver for outputting a data as the data output driver is activated in response to a first level of the input/output control signal.
摘要翻译：提供半导体存储器件。半导体存储器件包括：第一输入/输出控制单元，用于响应于激活与第一时钟信号的上升沿同步的数据的第一使能信号的激活，将感测节点改变为第一电平; 第二输入/输出控制单元，用于响应于延迟锁定时钟信号而将感测节点改变为第二电平，因为当第一使能信号和第二使能信号用于使能输出信号时，第二输入/输出控制单元被使能与时钟信号下降沿同步的数据被禁止; 用于输出输入/输出控制信号的输出单元; 并且响应于输入/输出控制信号的第一电平激活用于输出作为数据输出驱动器的数据的数据输出驱动器。

20. 发明授权

US07830731B2 Circuit for initializing a pipe latch unit in a semiconductor memory device 有权
标题翻译：用于在半导体存储器件中初始化管道锁存单元的电路
公开(公告)号：US07830731B2
公开(公告)日：2010-11-09
申请号：US12260298
申请日：2008-10-29
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C7/1039
摘要： A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An initialization controller controls the input controller and the output controller to thereby initialize the pipe latch unit in response to a read/write flag signal which is activated during a write operation.
摘要翻译：一种半导体存储器件包括具有用于锁存数据的多个管道锁存器的管道锁存单元。输入控制器控制从数据线发送到管道锁存单元的数据的输入定时。输出控制器控制锁存在管道锁存单元中的数据的输出定时。初始化控制器控制输入控制器和输出控制器，从而响应于在写操作期间被激活的读/写标志信号来初始化管锁存单元。

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