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11. 发明授权

US08237174B2 LED structure 有权
标题翻译： LED结构
公开(公告)号：US08237174B2
公开(公告)日：2012-08-07
申请号：US12776834
申请日：2010-05-10
申请人： Peng-Ren Chen , Hsueh-Hsing Liu , Jen-Inn Chyi
发明人： Peng-Ren Chen , Hsueh-Hsing Liu , Jen-Inn Chyi
IPC分类号： H01L27/15 , H01L31/12 , H01L33/00
CPC分类号： H01L33/14 , H01L33/04
摘要： The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0≦x≦1, 0≦y≦1, and 0≦x+y≦1.
摘要翻译：本发明公开了一种LED结构，其中N型电流扩展层插入在N型半导体层之间以均匀地分布流过N型半导体层的电流。 N型电流扩展层包括从低带隙到较高带隙的顺序堆叠的至少三个子层，其中具有较低带隙的子层在衬底附近，并且子层具有较高带隙的发光层靠近发光层。 N型电流扩展层的每个子层由通式In x Al y Ga（1-x-y）N表示，其中0＆nlE; x＆nlE; 1,0＆amp; nlE; y＆nlE; 1和0＆nlE; x + y＆nlE;

12. 发明申请

US20110271239A1 Lithography Performance Check Methods and Apparatus 有权
标题翻译：光刻性能检测方法与仪器
公开(公告)号：US20110271239A1
公开(公告)日：2011-11-03
申请号：US12770903
申请日：2010-04-30
申请人： Chi-Ta Lu , Peng-Ren Chen , Dong-Hsu Cheng , Chang-Jyh Hsieh
发明人： Chi-Ta Lu , Peng-Ren Chen , Dong-Hsu Cheng , Chang-Jyh Hsieh
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70
摘要： The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.
摘要翻译：本公开提供了许多不同的实施例。提供了一种掩模制造方法和系统。该方法和系统确定已经经历光学邻近校正的集成电路（IC）设计布局的关键区域。关键领域是受控IC设计布局的热点地区。然后对OPCed IC设计布局的关键区域进行光刻工艺检查。

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