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11. 发明授权

US08225123B2 Method and system for integrated circuit power supply management 有权
标题翻译：集成电路电源管理方法与系统
公开(公告)号：US08225123B2
公开(公告)日：2012-07-17
申请号：US12787402
申请日：2010-05-26
申请人： Sunny Gupta , Kumar Abhishek
发明人： Sunny Gupta , Kumar Abhishek
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D50/20
摘要： A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block.
摘要翻译：集成芯片中电源管理的方法和系统选择性地管理提供给集成电路内的各种电路的功率。集成电路包括组合逻辑块，存储块，电源块和控制块。电源模块包括多个功率调节器，用于产生各种幅度的电源电位。控制块接收掉电信号，时钟禁止信号和温度阈值信号，并且产生控制信号，以控制通过电源块提供给组合逻辑块和存储器块的电力的电位的大小。

12. 发明申请

US20130275936A1 INTEGRATED CIRCUIT POWER MANAGEMENT VERIFICATION METHOD 有权
标题翻译：集成电路电源管理验证方法
公开(公告)号：US20130275936A1
公开(公告)日：2013-10-17
申请号：US13447305
申请日：2012-04-16
申请人： Kumar Abhishek , Benjamin J. Ehlers , Sunny Gupta , Stefano Pietri
发明人： Kumar Abhishek , Benjamin J. Ehlers , Sunny Gupta , Stefano Pietri
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/62 , G06F2217/78 , G06F2217/84
摘要： A method for verifying power management of an integrated circuit design includes estimating a current load requirement of clocked modules in the circuit design based on the clock frequency and a predefined current load model. The voltage supplied to the circuit design is monitored. A first voltage regulator provides additional current drive to the circuit design when the supplied voltage drops below a threshold value of a full throttle run mode of the circuit design. A second voltage regulator is enabled to boost a response time of the first voltage regulator when the voltage drops below the threshold value.
摘要翻译：用于验证集成电路设计的电源管理的方法包括基于时钟频率和预定义的当前负载模型来估计电路设计中时钟模块的当前负载要求。监测供应给电路设计的电压。当所提供的电压低于电路设计的全油门运行模式的阈值时，第一电压调节器为电路设计提供额外的电流驱动。当电压下降到阈值以下时，第二电压调节器能够升高第一电压调节器的响应时间。

13. 发明授权

US08645886B2 Integrated circuit power management verification method 有权
标题翻译：集成电路电源管理验证方法
公开(公告)号：US08645886B2
公开(公告)日：2014-02-04
申请号：US13447305
申请日：2012-04-16
申请人： Kumar Abhishek , Benjamin J. Ehlers , Sunny Gupta , Stefano Pietri
发明人： Kumar Abhishek , Benjamin J. Ehlers , Sunny Gupta , Stefano Pietri
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F2217/62 , G06F2217/78 , G06F2217/84
摘要： A method for verifying power management of an integrated circuit design includes estimating a current load requirement of clocked modules in the circuit design based on the clock frequency and a predefined current load model. The voltage supplied to the circuit design is monitored. A first voltage regulator provides additional current drive to the circuit design when the supplied voltage drops below a threshold value of a full throttle run mode of the circuit design. A second voltage regulator is enabled to boost a response time of the first voltage regulator when the voltage drops below the threshold value.
摘要翻译：用于验证集成电路设计的电源管理的方法包括基于时钟频率和预定义的当前负载模型来估计电路设计中时钟模块的当前负载要求。监测供应给电路设计的电压。当所提供的电压低于电路设计的全油门运行模式的阈值时，第一电压调节器为电路设计提供额外的电流驱动。当电压下降到阈值以下时，第二电压调节器能够升高第一电压调节器的响应时间。

14. 发明授权

US08487805B1 Successive approximation analog-to-digital converter 有权
标题翻译：逐次近似模数转换器
公开(公告)号：US08487805B1
公开(公告)日：2013-07-16
申请号：US13403945
申请日：2012-02-23
申请人： Sunny Gupta , Kumar Abhishek , Kushal Kamal , Samaksh Sinha
发明人： Sunny Gupta , Kumar Abhishek , Kushal Kamal , Samaksh Sinha
IPC分类号： H03M1/34
CPC分类号： H03M1/007 , H03M1/46
摘要： An analog-to-digital converter (ADC) converts an analog input signal to a digital output signal by sampling an analog input signal to obtain an analog sample and then converting the analog sample to the digital output signal using a successive approximation algorithm. The method decreases ADC conversion time and increases ADC throughput.
摘要翻译：模数转换器（ADC）通过采样模拟输入信号将模拟输入信号转换为数字输出信号，以获得模拟采样，然后使用逐次逼近算法将模拟采样转换为数字输出信号。该方法可减少ADC转换时间并提高ADC吞吐量。

15. 发明申请

US20110296221A1 METHOD AND SYSTEM FOR INTEGRATED CIRCUIT POWER SUPPLY MANAGEMENT 有权
标题翻译：集成电路电源管理方法与系统
公开(公告)号：US20110296221A1
公开(公告)日：2011-12-01
申请号：US12787402
申请日：2010-05-26
申请人： Sunny GUPTA , Kumar Abhishek
发明人： Sunny GUPTA , Kumar Abhishek
IPC分类号： G06F1/32 , G05F1/10 , H03L7/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D50/20
摘要： A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block.
摘要翻译：集成芯片中电源管理的方法和系统选择性地管理提供给集成电路内的各种电路的功率。集成电路包括组合逻辑块，存储块，电源块和控制块。电源模块包括多个功率调节器，用于产生各种幅度的电源电位。控制块接收掉电信号，时钟禁止信号和温度阈值信号，并且产生控制信号，以控制通过电源块提供给组合逻辑块和存储器块的电力的电位的大小。

16. 发明授权

US08543856B2 Semiconductor device with wake-up unit 有权
标题翻译：具有唤醒单元的半导体器件
公开(公告)号：US08543856B2
公开(公告)日：2013-09-24
申请号：US13214164
申请日：2011-08-20
申请人： Shubhra Singh , Kumar Abhishek , Mukesh Bansal
发明人： Shubhra Singh , Kumar Abhishek , Mukesh Bansal
IPC分类号： G06F1/00 , G06F1/26
CPC分类号： G06F1/3206
摘要： A semiconductor device having a low power mode includes a buffer circuit associated with an interface pad, a power management controller (PMC), and a wakeup unit for waking up a part of the device from the low power mode. The buffer circuit is disabled in the low power mode by asserting a power on reset (POR) signal associated with the PMC. A wakeup signal is generated and provided to the wakeup unit from an analog power supply associated with the buffer circuit.
摘要翻译：具有低功率模式的半导体器件包括与接口焊盘相关联的缓冲电路，电源管理控制器（PMC）和用于从低功率模式唤醒器件的一部分的唤醒单元。通过断言与PMC相关联的上电复位（POR）信号，在低功耗模式下禁止缓冲电路。产生唤醒信号并从与缓冲电路相关联的模拟电源将其提供给唤醒单元。

17. 发明申请

US20130047016A1 SEMICONDUCTOR DEVICE WITH WAKE-UP UNIT 有权
标题翻译：具有唤醒单元的半导体器件
公开(公告)号：US20130047016A1
公开(公告)日：2013-02-21
申请号：US13214164
申请日：2011-08-20
申请人： Shubhra SINGH , Kumar Abhishek , Mukesh Bansal
发明人： Shubhra SINGH , Kumar Abhishek , Mukesh Bansal
IPC分类号： G06F1/32
CPC分类号： G06F1/3206
摘要： A semiconductor device having a low power mode includes a buffer circuit associated with an interface pad, a power management controller (PMC), and a wakeup unit for waking up a part of the device from the low power mode. The buffer circuit is disabled in the low power mode by asserting a power on reset (POR) signal associated with the PMC. A wakeup signal is generated and provided to the wakeup unit from an analog power supply associated with the buffer circuit.
摘要翻译：具有低功率模式的半导体器件包括与接口焊盘相关联的缓冲电路，电源管理控制器（PMC）和用于从低功率模式唤醒器件的一部分的唤醒单元。通过断言与PMC相关联的上电复位（POR）信号，在低功耗模式下禁止缓冲电路。产生唤醒信号并从与缓冲电路相关联的模拟电源将其提供给唤醒单元。

18. 发明申请

US20130339761A1 POWER MANAGEMENT SYSTEM FOR ELECTRONIC CIRCUIT 有权
标题翻译：电子电路电源管理系统
公开(公告)号：US20130339761A1
公开(公告)日：2013-12-19
申请号：US13525347
申请日：2012-06-17
申请人： Kumar Abhishek , Manmohan Rana , Samaksh Sinha
发明人： Kumar Abhishek , Manmohan Rana , Samaksh Sinha
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/3243 , H02J1/08 , H02J9/005 , H02J2001/008 , Y02D10/152 , Y02D50/20
摘要： A power management circuit for managing power supplied to an electronic circuit by a core power supply. The electronic circuit includes digital and analog circuit domains and operates in POWER-ON, RUN and STANDBY modes. The power management circuit includes a master state machine that exchanges a handshake signal with the analog circuit domain to monitor the modes of operation and generates first and second configuration signals. The power management circuit enables and disables the analog circuit domain based on the first and second configuration signals. A switch connected to the core power supply and the digital circuit module enables and disables the digital circuit domain based on the second configuration signal.
摘要翻译：一种用于管理由核心电源供应到电子电路的电力的电源管理电路。电子电路包括数字和模拟电路域，并在POWER-ON，RUN和STANDBY模式下工作。电源管理电路包括主状态机，其与模拟电路域交换握手信号以监视操作模式并产生第一和第二配置信号。电源管理电路基于第一和第二配置信号启用和禁用模拟电路域。连接到核心电源和数字电路模块的开关基于第二配置信号启用和禁用数字电路域。

19. 发明申请

US20110199139A1 FLIP-FLOP CIRCUIT WITH INTERNAL LEVEL SHIFTER 有权
标题翻译：具有内部水平移位的FLIP-FLOP电路
公开(公告)号：US20110199139A1
公开(公告)日：2011-08-18
申请号：US13097054
申请日：2011-04-29
申请人： Sunny ARORA , Kumar Abhishek , Mukesh Bansal , Shilpa Gupta
发明人： Sunny ARORA , Kumar Abhishek , Mukesh Bansal , Shilpa Gupta
IPC分类号： H03K3/289
CPC分类号： H03K3/356052 , H03K3/356121 , H03K3/356147
摘要： A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.
摘要翻译：具有内部电平移位器的触发器电路包括输入级，时钟输入级，输出级和电平转换级。输出级基于由输入级接收的输入信号和由时钟输入级接收的时钟信号产生输出信号。电平移位级使输出信号的电压电平上升。

20. 发明授权

US07543205B2 Control signal synchronization of a scannable storage circuit 有权
标题翻译：可扫描存储电路的控制信号同步
公开(公告)号：US07543205B2
公开(公告)日：2009-06-02
申请号：US11412532
申请日：2006-04-27
申请人： Kumar Abhishek
发明人： Kumar Abhishek
IPC分类号： G01R31/28 , H03K3/289
CPC分类号： G01R31/318594 , G01R31/31726
摘要： A system of control signal synchronization of a scannable storage circuit includes any number of storage circuits interconnected together with logic circuitry to form at least a portion of a functional circuit. Each of the storage circuits may include an input transmission gate to apply any one of a data input and a scan input to a storage element of the storage circuit based on an input circuitry that considers the state of the scan enable signal and a timing signal of a clock associated with the storage element. In addition, a control signal in a master latch of the storage element may synchronously close a hold loop in the master latch when the input transmission gate is opened upon the timing signal of the clock transitioning to a different state.
摘要翻译：可扫描存储电路的控制信号同步的系统包括与逻辑电路互连在一起的任何数量的存储电路，以形成功能电路的至少一部分。每个存储电路可以包括输入传输门，用于基于考虑扫描使能信号的状态的输入电路和数据输入和扫描输入的定时信号，将数据输入和扫描输入中的任一个应用于存储电路的存储元件与存储元件相关联的时钟。此外，当时钟转换到不同状态的定时信号打开输入传输门时，存储元件的主锁存器中的控制信号可以同步地闭合主锁存器中的保持环路。

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