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11. 发明授权

US5761149A Dynamic RAM 失效
标题翻译：动态RAM
公开(公告)号：US5761149A
公开(公告)日：1998-06-02
申请号：US679724
申请日：1996-07-12
申请人： Yukihide Suzuki , Kanehide Kenmizaki , Tsugio Takahashi , Masayuki Nakamura , Makoto Saeki , Chisa Makimura , Katsuo Komatsuzaki , Shunichi Sukegawa
发明人： Yukihide Suzuki , Kanehide Kenmizaki , Tsugio Takahashi , Masayuki Nakamura , Makoto Saeki , Chisa Makimura , Katsuo Komatsuzaki , Shunichi Sukegawa
IPC分类号： H01L27/108 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/418 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/105 , G11C8/00
CPC分类号： G11C29/80 , G11C11/418 , G11C29/83 , G11C8/14 , H01L27/105
摘要： A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.
摘要翻译：动态RAM具有主字线; 多个辅助字线，沿着与主字线交叉的位线的方向排列，多个动态存储单元被连接到该多个辅助字线; 多个副字选择线，其被延伸成与主字线垂直相交，并且通过该多个副字选择线发送用于选择多个辅助字线中的一个的选择信号; 以及用于从主字线接收选择信号的逻辑电路和来自每个辅助字选择线的选择信号，从而形成用于选择一个辅助字线的选择信号。在动态RAM中，当线处于未选择状态时，使主字线和副字选择线中的每一个的电压电平等于地电位。

12. 发明授权

US07092276B2 Series feram cell array 有权
公开(公告)号：US07092276B2
公开(公告)日：2006-08-15
申请号：US11048255
申请日：2005-01-31
申请人： Katsuo Komatsuzaki
发明人： Katsuo Komatsuzaki
IPC分类号： G11C11/22 , G11C11/42 , G11C5/06 , G11C7/00 , G11C8/00
CPC分类号： G11C11/22
摘要： Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.

13. 发明授权

US06944042B2 Multiple bit memory cells and methods for reading non-volatile data 有权
标题翻译：多位存储单元和用于读取非易失性数据的方法
公开(公告)号：US06944042B2
公开(公告)日：2005-09-13
申请号：US10334366
申请日：2002-12-31
申请人： Katsuo Komatsuzaki
发明人： Katsuo Komatsuzaki
IPC分类号： G11C11/14 , G11C11/22 , G11C11/56 , G11C5/06 , G11C7/00 , G11C11/00 , G11C11/34
CPC分类号： G11C11/14 , G11C11/22 , G11C11/5657
摘要： Memory cells are disclosed comprising volatile and non-volatile portions, where the non-volatile portions provide storage of multiple non-volatile data states or bits per memory cell. Methods are provided for reading non-volatile data states from a non-volatile portion of a memory cell into a volatile portion.
摘要翻译：公开了包含易失性和非易失性部分的存储器单元，其中非易失性部分提供多个非易失性数据状态或每个存储器单元的位的存储。提供了用于将非易失性数据状态从存储器单元的非易失性部分读入易失性部分的方法。

14. 发明授权

US06867997B2 Series feram cell array 有权
公开(公告)号：US06867997B2
公开(公告)日：2005-03-15
申请号：US10108810
申请日：2002-03-27
申请人： Katsuo Komatsuzaki
发明人： Katsuo Komatsuzaki
IPC分类号： G11C11/22 , G11C5/06 , G11C7/02 , G11C8/00
CPC分类号： G11C11/22
摘要： Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.

15. 发明授权

US06753202B2 CMOS photodiode having reduced dark current and improved light sensitivity and responsivity 有权
标题翻译： CMOS光电二极管具有降低的暗电流和改善的光敏度和响应性
公开(公告)号：US06753202B2
公开(公告)日：2004-06-22
申请号：US10446910
申请日：2003-05-28
申请人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
发明人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
IPC分类号： H01L2100
CPC分类号： H01L31/1126 , H01L27/14643 , H01L27/148
摘要： A method for the fabrication of a light-sensing diode in a high-resistivity semiconductor substrate. A high-energy implant of ions into the substrate is patterned to form an annular well of the same conductivity type as the substrate; followed by a second high-energy implant of the opposite conductivity type, within the center of the annulus; followed by a third implant, of lower energy and high dosage, to form a region of the first conductivity type extending laterally near the substrate surface. The resulting diode junction is thereby patterned to include two planes near the substrate surface, allowing incident light to traverse the junction twice.
摘要翻译：一种在高电阻率半导体衬底中制造感光二极管的方法。将高能量离子注入到衬底中被图案化以形成与衬底相同的导电类型的环形阱; 之后是相对导电类型的第二高能量植入在环的中心内; 随后是较低能量和高剂量的第三种植入物，以形成在衬底表面附近横向延伸的第一导电类型的区域。由此形成的二极管结被图案化以包括靠近衬底表面的两个平面，允许入射光穿过接合两次。

16. 发明授权

US06707702B1 Volatile memory with non-volatile ferroelectric capacitors 有权
标题翻译：具有非易失性铁电电容器的易失性存储器
公开(公告)号：US06707702B1
公开(公告)日：2004-03-16
申请号：US10293195
申请日：2002-11-13
申请人： Katsuo Komatsuzaki
发明人： Katsuo Komatsuzaki
IPC分类号： G11C1122
CPC分类号： G11C14/00
摘要： Memory apparatus and methods are provided for storing data in a semiconductor device, comprising volatile and non-volatile portions, where the non-volatile portion comprises two ferroelectric capacitors coupled with one of two internal nodes in the volatile memory portion. Apparatus is also disclosed wherein first and second ferroelectric capacitors are coupled with the first internal node of the volatile portion, and third and fourth ferroelectric capacitors are coupled with the second internal node of the volatile portion.
摘要翻译：提供存储装置和方法用于将数据存储在包括易失性和非易失性部分的半导体器件中，其中非易失性部分包括与易失性存储器部分中的两个内部节点之一耦合的两个铁电电容器。还公开了一种装置，其中第一和第二铁电电容器与易失性部分的第一内部节点耦合，第三和第四强电介质电容器与易失性部分的第二内部节点耦合。

17. 发明授权

US5498897A Transistor layout for semiconductor integrated circuit 失效
标题翻译：半导体集成电路晶体管布局
公开(公告)号：US5498897A
公开(公告)日：1996-03-12
申请号：US270085
申请日：1994-07-01
申请人： Katsuo Komatsuzaki , Masayasu Kawamura , Hidetoshi Iwai
发明人： Katsuo Komatsuzaki , Masayasu Kawamura , Hidetoshi Iwai
IPC分类号： H01L27/105 , H01L27/11 , H01L29/772
CPC分类号： H01L27/105 , Y10S257/927
摘要： A semiconductor integrated circuit comprising a MOSFET having a metal wiring layer formed via an insulating film above and along the gate electrode of the MOSFET. The MOSFET is structured such that its channel length is small or channel width is large, and an input signal is applied from at least both end sides of the gate electrode thereof. Since the metal wiring layer for the input signal is formed on the gate electrode of the MOSFET, high-speed operation is possible without increasing the layout area. FIG. 1.
摘要翻译：一种半导体集成电路，包括具有金属布线层的MOSFET，所述金属布线层经由MOSFET上方并沿着栅极电极的绝缘膜形成。 MOSFET的结构使得其沟道长度小或沟道宽度大，并且从其栅电极的至少两端侧施加输入信号。由于用于输入信号的金属布线层形成在MOSFET的栅电极上，因此可以在不增加布局面积的情况下进行高速运算。图。 1。

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