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11. 发明授权

US06249144B1 Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 有权
标题翻译：用于配置具有可变粒度组件的FPGA以提供对互连资源的时间共享访问的方法
公开(公告)号：US06249144B1
公开(公告)日：2001-06-19
申请号：US09669186
申请日：2000-09-25
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
IPC分类号： H03K19177
CPC分类号： H03K19/1737 , H01L2924/0002 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/17792 , H03K19/17796 , H01L2924/00
摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
摘要翻译：可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。这些可配置构建单元（CBE）中的未使用的组合被重新配置以执行进一步的逻辑功能来代替动态复用功能。每个CBE可以可编程地配置为提供不超过2对1的动态多路复用器（2：1 DyMUX）。然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。

12. 发明授权

US06216257B1 FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks 有权
标题翻译： FPGA设备和方法，其包括用于实现配置逻辑块的可变粒度功能架构和用于在配置逻辑块之间提供可配置路由的互补可变长度互连体系结构
公开(公告)号：US06216257B1
公开(公告)日：2001-04-10
申请号：US09603807
申请日：2000-06-26
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran , Bai Nguyen
IPC分类号： G06F1750
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17736 , H03K19/17756 , H03K19/17796
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resources of the VGA and VLI to efficiently pack function development into logic units of matched granularity and to transfer signals between logic units with interconnect lines of minimal length.
摘要翻译：具有多个行和列的逻辑功能单元的现场可编程门阵列器件（FPGA）以对称和互补的可变粒度架构（VGA）和可变长度互连架构（VLI）组织。综合映射利用VGA和VLI的多样化和对称资源，将功能开发有效地集成到匹配粒度的逻辑单元中，并在逻辑单元之间传输信号，并以最小长度的互连线传输信号。

13. 发明授权

US6100715A Methods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resources 有权
标题翻译：用于配置具有可变粒度块的FPGA的方法和用于提供对互连资源的时间共享访问的逻辑
公开(公告)号：US6100715A
公开(公告)日：2000-08-08
申请号：US212330
申请日：1998-12-15
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
IPC分类号： H03K19/173 , H03K19/177 , A03K19/177
CPC分类号： H03K19/17748 , H03K19/1737 , H03K19/17736 , H03K19/1778
摘要： A Variable Grain Architecture (VGA) includes a shared output component (SOC) that may be used for outputting different signals onto a shared longline within an FPGA. Plural VGB's make shared use of the SOC to out respective function signals to the shared longline.
摘要翻译：可变晶体结构（VGA）包括可用于将不同信号输出到FPGA内的共享长线上的共享输出组件（SOC）。多个VGB将共享的SOC用于将相应的功能信号分配给共享的延长线。

14. 发明授权

US06590415B2 Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 有权
标题翻译：用于配置具有可变粒度组件的FPGA以提供对互连资源的时间共享访问的方法
公开(公告)号：US06590415B2
公开(公告)日：2003-07-08
申请号：US09841209
申请日：2001-04-23
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
IPC分类号： G06F738
CPC分类号： H03K19/17736 , H03K19/1737
摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
摘要翻译：可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。这些可配置构建单元（CBE）的未使用的配置可重新配置以执行更多的逻辑功能来代替动态复用功能。每个CBE可以可编程配置为提供不超过2对1的动态多路复用器（2：1 DyMUX ）。然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。

15. 发明授权

US06211695B1 FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections 有权
标题翻译： FPGA集成电路具有嵌入式SRAM存储器块，具有注册的地址和数据输入部分
公开(公告)号：US06211695B1
公开(公告)日：2001-04-03
申请号：US09235615
申请日：1999-01-21
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
IPC分类号： G06F738
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has a registered address port for capturing received address signals in response to further-received, address-validating clock signals. Interconnect resources are provided for conveying the address-validating clock signals to address-changing circuitry so that a next address can be generated safely in conjunction with the capturing by the registered address port of a previous address signal.
摘要翻译：具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。每个嵌入式存储块具有用于响应于进一步接收的地址确认时钟信号来捕获接收到的地址信号的注册地址端口。提供互连资源用于将地址确认的时钟信号传送到地址改变电路，使得可以结合由先前地址信号的注册地址端口的捕获而安全地生成下一个地址。

16. 发明授权

US6127843A Dual port SRAM memory for run time use in FPGA integrated circuits 失效
标题翻译：双端口SRAM存储器用于运行时间用于FPGA集成电路
公开(公告)号：US6127843A
公开(公告)日：2000-10-03
申请号：US996049
申请日：1997-12-22
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes plural columns of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each logic function unit (VGB) is organized to process a nibble of data. Each embedded memory block is multi-ported and organized to store addressable nibbles of data. Interconnect resources are provided for efficiently transferring nibbles of data between the logic function units (VGB's) and corresponding memory blocks. Further interconnect resources (SVIC's) are provided for supplying address and control signals to each memory block. In one embodiment each memory block has at least one read-only port and at least one read/write port that are individually addressable and individually switchable into high output impedance tri-state modes.
摘要翻译：具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多列嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。每个逻辑功能单元（VGB）被组织以处理数据的半字节。每个嵌入式存储器块都是多端口的并被组织以存储可寻址的数据的半字节。提供互连资源，用于在逻辑功能单元（VGB）和相应的存储块之间有效传输数据的半字节。提供了进一步的互连资源（SVIC），用于向每个存储块提供地址和控制信号。在一个实施例中，每个存储器块具有至少一个只读端口和至少一个读/写端口，其可单独寻址并且可单独切换到高输出阻抗三态模式。

17. 发明授权

US06081473A FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode 有权
标题翻译：具有嵌入式sram存储器块的FPGA集成电路，每个具有静态和动态可控的读取模式
公开(公告)号：US06081473A
公开(公告)日：2000-06-27
申请号：US212331
申请日：1998-12-15
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals, including a read-mode (RMODE) control signal that switches the memory block between synchronous and asynchronous data transfer modes. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.
摘要翻译：具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。每个嵌入式存储块具有用于捕获接收到的地址信号的地址端口和用于捕获所提供的控制信号的控制端口，包括在同步和异步数据传输模式之间切换存储块的读模式（RMODE）控制信号。提供互连资源，包括用于以广播或窄播为基础将共享地址和控制信号传送到多个存储器块的存储器控制传送互连信道（MCIC）。

18. 发明授权

US6097212A Variable grain architecture for FPGA integrated circuits 失效
公开(公告)号：US6097212A
公开(公告)日：2000-08-01
申请号：US948306
申请日：1997-10-09
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/17792 , H03K19/17796 , H01L2924/0002
摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2xL, 4xL, 8xL and direct connect surround each super-VGB to provide different kinds of interconnect.

19. 发明授权

US06150842A Variable grain architecture for FPGA integrated circuits 失效
公开(公告)号：US06150842A
公开(公告)日：2000-11-21
申请号：US472645
申请日：1999-12-27
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/17792 , H03K19/17796 , H01L2924/0002
摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2.times.L, 4.times.L, 8.times.L and direct connect surround each super-VGB to provide different kinds of interconnect.

20. 发明授权

US06292930B1 Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources 失效
标题翻译：用于配置具有可变粒度块的FPGA的方法和用于提供对互连资源的时间共享访问的共享逻辑
公开(公告)号：US06292930B1
公开(公告)日：2001-09-18
申请号：US09603119
申请日：2000-06-22
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Giap H. Tran
IPC分类号： G06F1750
CPC分类号： H03K19/17752 , H03K19/1737 , H03K19/17736
摘要： A Variable Grain Architecture (VGA) includes a shared output component (SOC) that may be used for outputting different signals onto a shared longline within an FPGA. Plural VGB's make shared use of the SOC to out respective function signals to the shared longline.
摘要翻译：可变晶体结构（VGA）包括可用于将不同信号输出到FPGA内的共享长线上的共享输出组件（SOC）。多个VGB将共享的SOC用于将相应的功能信号分配给共享的延长线。

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