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11. 发明申请

US20090079058A1 Semiconductor substrate elastomeric stack 有权
标题翻译：半导体衬底弹性体叠层
公开(公告)号：US20090079058A1
公开(公告)日：2009-03-26
申请号：US11975007
申请日：2007-10-16
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/538 , H01L21/58
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that are directly surface mounted, as bare die, to a semiconductor substrate. Other semiconductor substrate assemblies of the stack involve bare memory integrated circuit dice that are directly surface mounted to a semiconductor substrate. Elastomeric connectors interconnect adjacent semiconductor substrates proceeding down the stack. Tines of novel comb-shaped power bus bar assembly structures extend into the stack to supply DC supply voltages. The supply voltages are supplied from bus bars, through vias in the semiconductor substrates, and to the integrated circuits on the other side of the substrates. The power bus bars also serve as capacitors and guides for liquid coolant.
摘要翻译：可重新配置的高性能计算机占用小于360立方英寸，并且具有每秒0.7 teraflops的近似计算能力，同时消耗少于1000瓦特。该计算机包括一组新的半导体衬底组件。一些半导体衬底组件涉及作为裸芯片直接表面安装到半导体衬底的现场可编程门阵列（FPGA）裸片。堆叠的其他半导体衬底组件包括直接表面安装到半导体衬底的裸存储器集成电路裸片。弹性连接器将相邻的半导体衬底互相连接，沿堆叠进入。新颖的梳状电源母线组合结构的齿条延伸到堆叠中以提供直流电源电压。电源电压由母线，半导体衬底中的通孔以及衬底另一侧的集成电路提供。电力母线还用作液体冷却剂的电容器和导轨。

12. 发明授权

US06998876B1 Coaxial clock tree for programmable logic devices 有权
标题翻译：可编程逻辑器件的同轴时钟树
公开(公告)号：US06998876B1
公开(公告)日：2006-02-14
申请号：US10820336
申请日：2004-04-08
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H03K19/00
CPC分类号： H03K5/15013 , G06F1/10 , H03K19/1774 , H03K19/1778
摘要： A balanced clock tree has a coaxial structure when a piece of the tree is viewed in cross-section. A plate is capacitively coupled to the inner conductor that runs down the center of the coaxial structure. This plate is usable to AC couple into the clock signal being propagated down the clock line. A programmable structure is disclosed for doing this whereby the clock signal is capacitively coupled from the clock line onto the input lead of a latch. The latch recreates the clock signal. The latch drives the recreated clock signal onto a local clock conductor. The structure is programmable in that it either couples the clock signal onto the local conductor or not depending on the state of a configuration bit in a memory cell of the programmable structure. In one embodiment, the clock tree can be tapped without substantially affecting signal propagation characteristics of the clock tree.
摘要翻译：当横截面看到一块树时，平衡时钟树具有同轴结构。平板电容耦合到沿着同轴结构的中心延伸的内部导体。该板可用于交流耦合到沿时钟线传播的时钟信号。公开了可编程结构，从而使时钟信号从时钟线电容耦合到锁存器的输入引线上。锁存器重新创建时钟信号。锁存器将重建的时钟信号驱动到本地时钟导体上。该结构是可编程的，其可以根据可编程结构的存储单元中的配置位的状态将时钟信号耦合到本地导体上。在一个实施例中，时钟树可以被抽头而基本上不影响时钟树的信号传播特性。

13. 发明授权

US06864156B1 Semiconductor wafer with well contacts on back side 有权
标题翻译：背面具有良好触点的半导体晶圆
公开(公告)号：US06864156B1
公开(公告)日：2005-03-08
申请号：US10407514
申请日：2003-04-04
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L21/20 , H01L21/30 , H01L21/306 , H01L21/8238 , H01L27/092 , H01L27/12
CPC分类号： H01L21/2007 , H01L21/823871 , H01L21/823892 , H01L27/0928 , H01L27/12
摘要： A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the gate of the transistor.
摘要翻译：将支撑结构晶片结合到部分或完全处理的器件晶片的上表面侧。器件晶片包括具有延伸到器件晶片的衬底材料中的阱区的晶体管。晶体管的源区和漏极区延伸到阱区。在安装支撑结构之后，装置晶片从后侧变薄直到达到井区的底部。为了减少源极和漏极结电容，可以继续蚀刻直到达到源极和漏极区域。在一个实施例中，在随后的蚀刻步骤中除去所有的阱到衬底结，从而减少或消除所得晶体管的阱到衬底结电容。阱电极和晶体管沟道之间的电阻降低，因为阱触点直接设置在晶体管的栅极正下方的器件晶片的背面。

14. 发明授权

US06789959B1 Fiber optic integrated circuit package using micromirrors 有权
标题翻译：使用微镜的光纤集成电路封装
公开(公告)号：US06789959B1
公开(公告)日：2004-09-14
申请号：US10377512
申请日：2003-02-27
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： G02B600
CPC分类号： G02B6/4292 , G02B6/3897 , G02B6/4214 , G02B6/4249
摘要： An external fiber optic cable is snap fit onto the connector of the integrated circuit package, light passes from an optical fiber in the external cable, through the first optical fiber and to the reflecting surface where the light is reflected by the reflecting surface so that it is incident on the photodetector whereas the photodetector converts the light into an electrical signal and the electrical signal is then communicated via a micro pad structures from the optoelectronic die.
摘要翻译：外部光缆被卡扣配合到集成电路封装的连接器上，光从外部电缆中的光纤通过第一光纤到反射表面，光被反射表面反射，入射到光电检测器上，而光电检测器将光转换成电信号，然后经由微电子管芯的微焊盘结构传送电信号。

15. 发明授权

US06219305B1 Method and system for measuring signal propagation delays using ring oscillators 失效
标题翻译：使用环形振荡器测量信号传播延迟的方法和系统
公开(公告)号：US06219305B1
公开(公告)日：2001-04-17
申请号：US09114369
申请日：1998-07-14
申请人： Robert D. Patrie , Robert W. Wells , Steven P. Young , Christopher H. Kingsley , Daniel Chung , Robert O. Conn
发明人： Robert D. Patrie , Robert W. Wells , Steven P. Young , Christopher H. Kingsley , Daniel Chung , Robert O. Conn
IPC分类号： G04F800
CPC分类号： G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反相反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。这些信号转换在预定的时间周期内进行计数以建立振荡器的平均周期。最后，振荡器的平均周期与通过测试电路的平均信号传播延迟有关。本发明的一个实施例包括相位鉴别器，其对振荡器的输出进行采样并累加表示该信号的占空比的数据。然后可以将占空比与测试信号的平均周期组合，以分别确定与通过测试电路传播的下降沿和上升沿相关联的延迟。

16. 发明授权

US06204815B1 Increased propagation speed across integrated circuits 有权
标题翻译：跨集成电路增加传播速度
公开(公告)号：US06204815B1
公开(公告)日：2001-03-20
申请号：US09302587
申请日：1999-04-30
申请人： Austin H. Lesea , Robert O. Conn
发明人： Austin H. Lesea , Robert O. Conn
IPC分类号： H01Q138
CPC分类号： H01Q21/0037 , H01Q1/38
摘要： The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit. Antenna/receiver circuit pairs are disposed at various locations across the surface of the integrated circuit where the signal is to be received and used. Other methods and embodiments are disclosed.
摘要翻译：在集成电路中的导体上行进的电信号的最大传播速度受到围绕导体的电介质材料的介电常数的限制。不是通过介电常数为两个或两个以上的介电材料包围的导体传输电信号，而是以跨越整个集成电路表面的高速通过空气传播信号作为电磁波。在一个实施例中，射频（RF）信号经由传输线路传递到集成电路封装中。传输线将RF信号提供给设置在封装内的集成电路上方的波导状结构。 RF信号通过波导结构中的空气通过集成电路的上表面传播作为电磁波。天线/接收器电路对设置在集成电路的要被接收和使用信号的表面的各个位置处。公开了其它方法和实施例。

17. 发明授权

US5923614A Structure and method for reading blocks of data from selectable points in a memory device 失效
标题翻译：用于从存储器件中的可选点读取数据块的结构和方法
公开(公告)号：US5923614A
公开(公告)日：1999-07-13
申请号：US71144
申请日：1998-04-30
申请人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
发明人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
IPC分类号： G11C8/04 , H03K19/177 , G11C8/00 , G06F7/38
CPC分类号： H03K19/17772 , G11C8/04 , H03K19/1776
摘要： A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.
摘要翻译：提供了自寻址存储器件，其可以从设备中的多于一个初始位置开始提供数据块，并且可以具有在任一方向上读取的选项。该存储设备可以有效地存储用于配置一个或多个可配置逻辑设备的多个可能具有不同大小的比特流。可以以任何顺序访问每个存储的比特流。在一个实施例中，可配置逻辑器件是现场可编程门阵列（“FPGA”）。在一个实施例中，存储器件是从全零读取或从全部读取的只读存储器（“ROM”）。在一个实施例中，ROM包括允许级联多个ROM的双向芯片使能链。

18. 发明授权

US08404585B2 Preventing breakage of long metal signal conductors on semiconductor substrates 有权
标题翻译：防止半导体基板上的长金属信号导体断裂
公开(公告)号：US08404585B2
公开(公告)日：2013-03-26
申请号：US13135510
申请日：2011-07-07
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L21/44
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigaPascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius.
摘要翻译：一种装置包括设置在半导体衬底的顶表面上的绝缘体体积，软电介质管和金属导体。绝缘体具有大于约3千兆帕（gPa）的硬度，软电介质具有小于3gPa的硬度。软电介质管和金属导体都嵌入在绝缘体的体积内。管限定中心体积，并且金属导体沿着穿过中心体积的方向延伸至少一英寸的距离。当在垂直于该方向的横截面中观察装置时，金属导体被软电介质环绕。金属导体可以包括多个弯曲部分。当设备在零度至摄氏度摄氏八十度的范围内温度循环时，金属导体不会断裂。

19. 发明授权

US07944041B2 Integrated semiconductor substrate structure using incompatible processes 有权
公开(公告)号：US07944041B2
公开(公告)日：2011-05-17
申请号：US11975966
申请日：2007-10-22
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/52
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes. The first portion is a signal interconnect structure containing a thin conductor layers portion characterized as having a plurality of thin, fine-pitch conductors. The second portion is a power connection structure that includes thick conductors and vertical through-holes. The through-holes contain conductive material and supply power to the FPGA dice from power bus bars located at the other side of the semiconductor substrate. The portions are joined at the wafer level by polishing the wafer surfaces within a few atoms of flatness and subsequent cleaning. The portions are then fusion bonded together or combined using an adhesive material.

20. 发明申请

US20100187665A1 Integral metal structure with conductive post portions 有权
标题翻译：具有导电柱部分的整体金属结构
公开(公告)号：US20100187665A1
公开(公告)日：2010-07-29
申请号：US12321833
申请日：2009-01-26
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/48 , H01L21/302 , H01L21/31
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.
摘要翻译：多个FPGA管芯设置在半导体衬底上。为了提供多个FPGA芯片所需的巨大功率，功率从位于半导体衬底另一侧的厚金属层和大的整体金属结构垂直地穿过半导体衬底。由于半导体衬底与与衬底接触的金属层具有不同的热线性膨胀系数，所以当结构经受温度变化时，可能发生分层。为了防止与半导体衬底连接并与整体金属结构电接触的金属层的分层，整体金属结构被制成具有一定数量的柱部分。在温度变化期间，整体金属结构的后部相对于连接到半导体衬底的金属层弯曲和滑动，并且防止否则会引起分层的线性应力。

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