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11. 发明申请

US20130132755A1 POWER MANAGEMENT OF LOW POWER LINK STATES 有权
标题翻译：低功率链路状态的电源管理
公开(公告)号：US20130132755A1
公开(公告)日：2013-05-23
申请号：US13725880
申请日：2012-12-21
申请人： Barnes Cooper , Jaya L. Jeyaseelan , Robert E. Gough
发明人： Barnes Cooper , Jaya L. Jeyaseelan , Robert E. Gough
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/3228 , G06F1/3253 , G06F1/3287 , Y02D10/151 , Y02D50/20
摘要： A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
摘要翻译：一种用于低功率链路状态智能电源管理的方法和装置。一些实施例包括用于经由链路耦合到控制器的设备的方法，设备和系统; 链路功率管理引擎，用于基于事务改变链路的功率状态以及对设备和控制器之间的未来事务的一些知识; 以及用于存储链路电源管理引擎的存储器或逻辑。在一些实施例中，存储器存储关于以下至少一个的信息：链路的功率状态，设备缓冲，控制器或设备状态或事务历史。在一些实施例中，设备是计算机系统的外设。在一些实施例中，该方法可以包括将设备转换到各种链路状态。描述其他实施例。

12. 发明授权

US07984314B2 Power management of low power link states 有权
标题翻译：低功率链路状态的电源管理
公开(公告)号：US07984314B2
公开(公告)日：2011-07-19
申请号：US11906007
申请日：2007-09-29
申请人： Barnes Cooper , Jaya L. Jeyaseelan , Robert E. Gough
发明人： Barnes Cooper , Jaya L. Jeyaseelan , Robert E. Gough
IPC分类号： G06F1/00
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/3228 , G06F1/3253 , G06F1/3287 , Y02D10/151 , Y02D50/20
摘要： A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
摘要翻译：一种用于低功率链路状态智能电源管理的方法和装置。一些实施例包括用于经由链路耦合到控制器的设备的方法，设备和系统; 链路功率管理引擎，用于基于事务改变链路的功率状态以及对设备和控制器之间的未来事务的一些知识; 以及用于存储链路电源管理引擎的存储器或逻辑。在一些实施例中，存储器存储关于以下至少一个的信息：链路的功率状态，设备缓冲，控制器或设备状态或事务历史。在一些实施例中，设备是计算机系统的外设。在一些实施例中，该方法可以包括将设备转换到各种链路状态。描述其他实施例。

13. 发明申请

US20150277778A1 VIRTUAL GENERAL-PURPOSE I/O CONTROLLER 有权
标题翻译：虚拟通用I / O控制器
公开(公告)号：US20150277778A1
公开(公告)日：2015-10-01
申请号：US14227735
申请日：2014-03-27
申请人： Nicholas J. Adams , Robert E. Gough , Sai Prasad Paithara Balagangadhara , Pronay Dutta
发明人： Nicholas J. Adams , Robert E. Gough , Sai Prasad Paithara Balagangadhara , Pronay Dutta
IPC分类号： G06F3/06 , G06F13/24
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0673 , G06F13/105 , G06F13/24 , G06F13/385
摘要： Technologies for virtual general purpose I/O (GPIO) include a computing device having a virtual GPIO controller driver, a virtual GPIO controller firmware interface, and a virtual GPIO controller. The driver receives a GPIO command from an operating system of the computing device. The GPIO command specifies an operation to be performed by a GPIO pin. The driver sends the GPIO command to the firmware interface. In response to the firmware interface receiving the command, the virtual GPIO controller emulates a virtual GPIO pin to implement the GPIO command. The firmware interface may trigger an interrupt that can be received by the operating system. The virtual GPIO controller may emulate the virtual GPIO pin using firmware-reserved backing memory, an embedded controller, or an interface to a peripheral device of the computing device. The firmware interface may be an ACPI control method. Other embodiments are described and claimed.
摘要翻译：用于虚拟通用I / O（GPIO）的技术包括具有虚拟GPIO控制器驱动程序，虚拟GPIO控制器固件接口和虚拟GPIO控制器的计算设备。驱动程序从计算设备的操作系统接收GPIO命令。 GPIO命令指定要由GPIO引脚执行的操作。驱动程序将GPIO命令发送到固件界面。响应固件接口接收命令，虚拟GPIO控制器仿真虚拟GPIO引脚来实现GPIO命令。固件接口可能会触发操作系统可以接收的中断。虚拟GPIO控制器可以使用固件保留后备内存，嵌入式控制器或与计算设备的外围设备的接口来模拟虚拟GPIO引脚。固件接口可以是ACPI控制方法。描述和要求保护其他实施例。

14. 发明申请

US20160252943A1 DYNAMICALLY UPDATING LOGICAL IDENTIFIERS OF CORES OF A PROCESSOR 有权
标题翻译：动态更新处理器的逻辑逻辑标识符
公开(公告)号：US20160252943A1
公开(公告)日：2016-09-01
申请号：US14633455
申请日：2015-02-27
申请人： Ankush Varma , Krishnakanth V. Sistla , Guy G. Sotomayor , Andrew D. Henroid , Robert E. Gough , Tod F. Schiff
发明人： Ankush Varma , Krishnakanth V. Sistla , Guy G. Sotomayor , Andrew D. Henroid , Robert E. Gough , Tod F. Schiff
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F15/00 , G06F1/206 , G06F1/26 , G06F1/3243 , G06F9/45541 , G06F9/45558 , G06F9/5077 , G06F2009/4557 , Y02D10/152 , Y02D10/16
摘要： In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心，每个核心包括存储用于核心的物理标识符的第一存储器和存储与所述核心相关联的逻辑标识符的第二存储器; 多个热传感器，用于测量处理器相应位置处的温度; 以及功率控制器，其包括动态核心标识符逻辑，用于至少部分地基于与所述第一核相关联的温度来动态地重新映射与第一核相关联的第一逻辑标识符以将所述第一逻辑标识符与第二核相关联，所述动态重映射以使第一线程从第一核心迁移到第二核心到操作系统。描述和要求保护其他实施例。

15. 发明授权

US08689028B2 Method and apparatus to reduce idle link power in a platform 有权
标题翻译：降低平台空闲链路功率的方法和装置
公开(公告)号：US08689028B2
公开(公告)日：2014-04-01
申请号：US13175574
申请日：2011-07-01
申请人： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
发明人： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要： A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
摘要翻译：一种降低平台空闲链路功率的方法和装置。在本发明的一个实施例中，主机及其在平台中的耦合端点各自具有低功率空闲链路状态，其允许在主机及其耦合的端点中禁用高速链路电路。这允许平台减少其空闲功率，因为在本发明的一个实施例中，主机及其耦合端点能够关闭其高速链路电路。

16. 发明申请

US20140068135A1 Providing A Consolidated Sideband Communication Channel Between Devices 审中-公开
标题翻译：在设备之间提供合并边带通信通道
公开(公告)号：US20140068135A1
公开(公告)日：2014-03-06
申请号：US14011009
申请日：2013-08-27
申请人： David J. Harriman , Mahesh Wagh , Robert E. Gough , James E. Jaussi
发明人： David J. Harriman , Mahesh Wagh , Robert E. Gough , James E. Jaussi
IPC分类号： G06F13/40
CPC分类号： G06F13/4027 , G06F1/3203 , G06F13/20 , G06F13/4295 , G06N99/005 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有事务层和链路层的协议栈。另外，第一物理（PHY）单元被耦合到协议栈，以经由物理链路提供处理器和耦合到处理器的设备之间的通信，其中第一PHY单元是低功率通信协议，并且包括第一物理单位电路。反过来，第二PHY单元被耦合到协议栈，以经由耦合在与物理链路分离的多核处理器和设备之间的边带信道来提供处理器和设备之间的通信，其中第二PHY单元包括第二物理单元电路。描述和要求保护其他实施例。

17. 发明授权

US08607075B2 Idle duration reporting for power management 有权
标题翻译：电源管理空闲时间报告
公开(公告)号：US08607075B2
公开(公告)日：2013-12-10
申请号：US12347573
申请日：2008-12-31
申请人： Robert E. Gough , Seh W. Kwa , Neil W. Songer , Jaya L. Jeyaseelan , Barnes Cooper
发明人： Robert E. Gough , Seh W. Kwa , Neil W. Songer , Jaya L. Jeyaseelan , Barnes Cooper
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3215 , G06F1/3228
摘要： For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，可以接收对应于一个或多个下游设备的空闲持续时间的数据。可以至少部分地基于所接收的数据来管理功率。还公开了其他实施例。

18. 发明授权

US08601296B2 Downstream device service latency reporting for power management 有权
标题翻译：用于电源管理的下游设备服务延迟报告
公开(公告)号：US08601296B2
公开(公告)日：2013-12-03
申请号：US12346853
申请日：2008-12-31
申请人： Jaya L. Jeyaseelan , Jim Walsh , Robert E. Gough , Barnes Cooper , Neil W. Songer
发明人： Jaya L. Jeyaseelan , Jim Walsh , Robert E. Gough , Barnes Cooper , Neil W. Songer
IPC分类号： G06F1/26 , G06F1/00 , G06F3/00 , G06F13/00 , G06F13/42 , H04L12/26
CPC分类号： H04W52/0225 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3296 , G06F13/4282 , H04L43/0858 , Y02D10/151 , Y02D70/00 , Y02D70/142 , Y02D70/23
摘要： For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，可以识别对于下游设备的至少一部分从第一状态到第二不同状态的转变。第一和第二状态可以对应于与下游设备的至少一部分的活动有关的不同级别。响应于所识别的一个或多个上游设备的转换，至少部分地基于服务等待时间来对应于服务等待时间的数据可被发送到上游设备以管理电力。还公开了其他实施例。

19. 发明授权

US08549205B1 Providing a consolidated sideband communication channel between devices 有权
公开(公告)号：US08549205B1
公开(公告)日：2013-10-01
申请号：US13477304
申请日：2012-05-22
申请人： David J. Harriman , Mahesh Wagh , Robert E. Gough , James E. Jaussi
发明人： David J. Harriman , Mahesh Wagh , Robert E. Gough , James E. Jaussi
IPC分类号： G06F13/20
CPC分类号： G06F13/4027 , G06F1/3203 , G06F13/20 , G06F13/4295 , G06N99/005 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

20. 发明授权

US08341445B2 Power management of electronic devices using transitions between link states based on device activity 有权
标题翻译：使用基于设备活动的链路状态之间的转换的电子设备的电源管理
公开(公告)号：US08341445B2
公开(公告)日：2012-12-25
申请号：US13186322
申请日：2011-07-19
申请人： Barnes Cooper , Jaya L. Jeyaseelan , Robert E. Gough
发明人： Barnes Cooper , Jaya L. Jeyaseelan , Robert E. Gough
IPC分类号： G06F1/00
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/3228 , G06F1/3253 , G06F1/3287 , Y02D10/151 , Y02D50/20
摘要： A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
摘要翻译：一种用于低功率链路状态智能电源管理的方法和装置。一些实施例包括用于经由链路耦合到控制器的设备的方法，设备和系统; 链路功率管理引擎，用于基于事务改变链路的功率状态以及对设备和控制器之间的未来事务的一些知识; 以及用于存储链路电源管理引擎的存储器或逻辑。在一些实施例中，存储器存储关于以下至少一个的信息：链路的功率状态，设备缓冲，控制器或设备状态或事务历史。在一些实施例中，设备是计算机系统的外设。在一些实施例中，该方法可以包括将设备转换到各种链路状态。描述其他实施例。

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