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11. 发明授权

US08868396B1 Verification and debugging using heterogeneous simulation models 有权
标题翻译：使用异构仿真模型进行验证和调试
公开(公告)号：US08868396B1
公开(公告)日：2014-10-21
申请号：US12605077
申请日：2009-10-23
申请人： Nabeel Shirazi , L. James Hwang , Chi Bun Chan , Hem C. Neema , Kumar Deepak
发明人： Nabeel Shirazi , L. James Hwang , Chi Bun Chan , Hem C. Neema , Kumar Deepak
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.
摘要翻译：本文公开了一种用于验证和调试高级编程系统的电路设计模块的方法和装置。在高级编程环境中创建的电路设计必须经过多次转换，因为它被编译成可以在硬件中实现的形式。在每个变换步骤中，必须用仿真模型验证电路的行为，并且如果转换改变了电路的行为，则进行调试。所要求保护的发明提出了一种用于在不同仿真模型之间验证和调试的新方法，并通过利用高级电路设计的模块化结构来实现本领域的进步，以系统地识别不同仿真模型之间的模拟不匹配并确定电路的哪些部分设计负责的差异。

12. 发明授权

US08102188B1 Method of and system for implementing a circuit in a device having programmable logic 有权
标题翻译：用于在具有可编程逻辑的设备中实现电路的方法和系统
公开(公告)号：US08102188B1
公开(公告)日：2012-01-24
申请号：US12757770
申请日：2010-04-09
申请人： Chi Bun Chan , Nabeel Shirazi
发明人： Chi Bun Chan , Nabeel Shirazi
IPC分类号： H03K19/173
CPC分类号： H03K19/17756 , H03K19/1776
摘要： A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory is disclosed. The method comprises configuring the programmable resources of the device with a circuit design; storing a first page of data in a block of random access memory; determining a page fault while interfacing with the block of random access memory when implementing the circuit design; performing a partial reconfiguration of the device, wherein a second page of data is stored in the block of random access memory; and accessing the second page of data. A system of implementing a circuit in a device having programmable logic is also disclosed.
摘要翻译：公开了一种在具有可编程资源和预定量的可用内部存储器的设备中实现电路的方法。该方法包括利用电路设计来配置设备的可编程资源; 将第一页数据存储在随机存取存储器块中; 当实现电路设计时，确定页面错误同时与随机存取存储器块接口; 执行所述设备的部分重新配置，其中第二数据页被存储在所述随机存取存储器块中; 并访问第二页数据。还公开了一种在具有可编程逻辑的设备中实现电路的系统。

13. 发明授权

US08402442B1 Common debugger method and system 有权
标题翻译：常用的调试器方法和系统
公开(公告)号：US08402442B1
公开(公告)日：2013-03-19
申请号：US12510810
申请日：2009-07-28
申请人： Chi Bun Chan , Jingzhao Ou , Nabeel Shirazi
发明人： Chi Bun Chan , Jingzhao Ou , Nabeel Shirazi
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F11/267 , G06F11/3664
摘要： Disclosed are approaches for operating a plurality of debugger tools. A common debugger receives first-type commands for processing. Each first-type command references one of the debugger tools. Each debugger tool provides control over a respective set of one or more components of the electronic system and recognizes a respective set of tool-specific commands. Each input first-type command is translated into a respective tool-specific command that is compatible with the one of the debugger tools specified in the first-type command. Each respective tool-specific command from the common debugger is provided to the one of the debugger tools specified in the input first-type command from which the respective tool-specific command was translated. Each translated tool-specific command is performed by the targeted debugger tool.
摘要翻译：公开了用于操作多个调试器工具的方法。一个常见的调试器接收第一个类型的命令进行处理。每个first-type命令引用一个调试器工具。每个调试器工具提供对电子系统的一个或多个组件的相应集合的控制，并识别相应的一组工具特定命令。每个输入第一类型命令被转换成与第一类型命令中指定的调试器工具兼容的相应的特定于工具的命令。来自公共调试器的每个相应的特定于工具的命令被提供给转换相应的特定于工具的命令的输入第一类型命令中指定的调试器工具之一。每个翻译的特定于工具的命令都由目标调试工具执行。

14. 发明授权

US08265918B1 Simulation and emulation of a circuit design 有权
标题翻译：电路设计的仿真和仿真
公开(公告)号：US08265918B1
公开(公告)日：2012-09-11
申请号：US12579846
申请日：2009-10-15
申请人： Hem C. Neema , Chi Bun Chan , Kumar Deepak , Nabeel Shirazi
发明人： Hem C. Neema , Chi Bun Chan , Kumar Deepak , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5022
摘要： Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.
摘要翻译：协同仿真平台通常包括基于软件的系统和基于硬件的系统，其中电路设计的不同部分在基于软件的系统中模拟或在基于硬件的系统上仿真。在电路设计模型可以共同模拟之前，电路设计必须被转换和配置成可以与特定的基于硬件的系统执行和接口的形式。本发明的实施例提供了一种用于对电路设计的一部分进行协同仿真的方法，系统和制品，并且通过改进协同仿真配置和设置并提供协同仿真调整能力来实现本领域的进步运行。

15. 发明授权

US07937259B1 Variable clocking in hardware co-simulation 有权
标题翻译：硬件协同仿真可变时钟
公开(公告)号：US07937259B1
公开(公告)日：2011-05-03
申请号：US12002838
申请日：2007-12-18
申请人： Chi Bun Chan , Bradley L. Taylor , Nabeel Shirazi
发明人： Chi Bun Chan , Bradley L. Taylor , Nabeel Shirazi
IPC分类号： G06F9/455
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Various embodiments of a co-simulation system are disclosed. In one embodiment, a data processing arrangement executes a simulator that simulates a first block of an electronic circuit design. A first clock source generates a first clock signal, and a second clock source generates a second clock signal. The first and second clock signals are independent one from another, and an operating frequency of the second clock signal is dynamically adjustable from a clock control interface. A programmable logic device (PLD) is configured with logic that includes a co-simulation interface clocked by the first clock signal, a second block of the electronic circuit design that is clocked by the second clock signal, and a synchronizer that controls data transmission between the co-simulation interface and the second block.
摘要翻译：公开了共模拟系统的各种实施例。在一个实施例中，数据处理装置执行模拟电子电路设计的第一块的模拟器。第一时钟源产生第一时钟信号，第二时钟源产生第二时钟信号。第一和第二时钟信号彼此独立，并且第二时钟信号的工作频率可以从时钟控制接口动态地调整。可编程逻辑器件（PLD）配置有逻辑，逻辑包括由第一时钟信号定时的协同仿真接口，由第二时钟信号计时的电子电路设计的第二块，以及控制数字传输的同步器共模仿界面和第二块。

16. 发明授权

US07746099B1 Method of and system for implementing a circuit in a device having programmable logic 有权
标题翻译：用于在具有可编程逻辑的设备中实现电路的方法和系统
公开(公告)号：US07746099B1
公开(公告)日：2010-06-29
申请号：US12008489
申请日：2008-01-11
申请人： Chi Bun Chan , Nabeel Shirazi
发明人： Chi Bun Chan , Nabeel Shirazi
IPC分类号： H03K19/173
CPC分类号： H03K19/17756 , H03K19/1776
摘要： A method of implementing a circuit in a device having programmable logic is disclosed. The method comprises implementing a circuit in the programmable logic of the device; storing data in a block of random access memory; performing a partial reconfiguration of the device, where new data is stored in the block of random access memory; and accessing the new data. A system of implementing a circuit in a device having programmable logic is also disclosed.
摘要翻译：公开了一种在具有可编程逻辑的装置中实现电路的方法。该方法包括在设备的可编程逻辑中实现电路; 将数据存储在随机存取存储器块中; 执行所述设备的部分重新配置，其中新数据被存储在所述随机存取存储器块中; 并访问新数据。还公开了一种在具有可编程逻辑的设备中实现电路的系统。

17. 发明授权

US08650517B1 Automatically documenting circuit designs 有权
标题翻译：自动记录电路设计
公开(公告)号：US08650517B1
公开(公告)日：2014-02-11
申请号：US12581631
申请日：2009-10-19
申请人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
发明人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.
摘要翻译：在包括处理器和存储器的系统中，自动记录电路设计的方法可以包括确定高级建模系统（HLMS）电路设计的用户评论实体（UCE）对HLMS电路的HLMS块的分配将HLMS电路设计的每个HLMS块转换为HLMS块的硬件描述语言（HDL）表示，并且对于分配了UCE的每个HLMS块，由处理器在HDL表示内插入，将UCE的内容以注释的形式分配给HLMS块。 HDL表示可以存储在内存中。

18. 发明授权

US08417965B1 Method and circuit for secure definition and integration of cores 有权
标题翻译：核心的安全定义和集成的方法和电路
公开(公告)号：US08417965B1
公开(公告)日：2013-04-09
申请号：US12755760
申请日：2010-04-07
申请人： Arvind Sundararajan , Chi Bun Chan , Nabeel Shirazi
发明人： Arvind Sundararajan , Chi Bun Chan , Nabeel Shirazi
IPC分类号： G06F11/30 , G06F12/14 , G06F7/04 , G06F17/30 , G06F9/445 , H04L29/06 , H04L9/00 , H04L9/30 , H04K1/00 , H04N7/16
CPC分类号： G06F17/505 , G06F11/3664 , G06F17/5054 , H04L9/0825 , H04L9/0877 , H04L63/0478
摘要： An embodiment of the present invention provides a method and circuit for secure definition and integration of a core into a circuit design without exposing the core. In one embodiment, a core development package is obtained. The core development package includes an encrypted core and a decryption key of the encrypted core. The decryption key is encrypted with an asymmetric cipher. The encrypted core is transmitted from the design tool to a trusted platform module. The decryption key is decrypted with a private key of the asymmetric cipher. The encrypted core is decrypted within the trusted platform module. One or more design tool operations are performed using the decrypted core.
摘要翻译：本发明的一个实施例提供了一种用于将核心安全地定义和集成到电路设计中而不暴露核心的方法和电路。在一个实施例中，获得核心开发包。核心开发包包括加密核心和加密核心的解密密钥。解密密钥用非对称密码加密。加密核心从设计工具传输到可信平台模块。解密密钥用非对称密码的私钥解密。加密核心在可信平台模块内被解密。使用解密的核执行一个或多个设计工具操作。

19. 发明授权

US08248869B1 Configurable memory map interface and method of implementing a configurable memory map interface 有权
标题翻译：可配置的存储器映射接口和实现可配置存储器映射接口的方法
公开(公告)号：US08248869B1
公开(公告)日：2012-08-21
申请号：US12581099
申请日：2009-10-16
申请人： Chi Bun Chan , Jingzhao Ou
发明人： Chi Bun Chan , Jingzhao Ou
IPC分类号： G11C7/00
CPC分类号： G06F12/0646 , G11C7/1009 , G11C7/1012 , G11C2029/1806 , G11C2029/5602
摘要： A configurable memory map interface coupled to a circuit element having input/output ports is disclosed. The configurable memory map interface comprises an input coupled to receive an address enabling reading from or writing to the circuit element; a memory storing enable signal parameters, the enable signal parameters controlling timing of enable signals for the reading from or the writing to the circuit element; and an enable signal generator generating the enable signals enabling the reading from or the writing to the circuit element based upon the enable signal parameters stored in the memory. A method of implementing a configurable memory map interface is also disclosed.
摘要翻译：公开了一种耦合到具有输入/输出端口的电路元件的可配置存储器映射接口。可配置存储器映射接口包括耦合以接收能够读取或写入电路元件的地址的输入; 存储器使能信号参数的存储器，所述使能信号参数控制用于从所述电路元件读取或写入所述电路元件的使能信号的定时; 以及使能信号发生器，其基于存储在存储器中的使能信号参数，产生使能信号，使得能够读取或写入电路元件。还公开了一种实现可配置存储器映射接口的方法。

20. 发明授权

US07992111B1 Conversion of a high-level graphical circuit design block to a high-level language program 有权
标题翻译：将高级图形电路设计块转换为高级语言程序
公开(公告)号：US07992111B1
公开(公告)日：2011-08-02
申请号：US12467678
申请日：2009-05-18
申请人： Haibing Ma , Jingzhao Ou , Chi Bun Chan
发明人： Haibing Ma , Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F9/45
CPC分类号： G06F8/34
摘要： Approaches for processing an electronic circuit design. In one embodiment, the graphical model of an outer subsystem block and an inner subsystem block are translated into a high-level language (HLL) program. The HLL program includes a specification of a first function corresponding to the outer subsystem block and within the specification of the first function a specification of a second function corresponding to the inner subsystem block. The specification of the first function references a parameter of the outer subsystem block and specifies invocation of the second function. The specification of the second function specifies invocation of a third function corresponding to a leaf block in the inner subsystem block. The specification of the first function references a variable corresponding to the parameter, and that variable is referenced by the second or third functions. Execution of the HLL program instantiates a model of the design.
摘要翻译：处理电子电路设计的方法。在一个实施例中，外部子系统块和内部子系统块的图形模型被转换为高级语言（HLL）程序。 HLL程序包括与外部子系统块相对应的第一功能的规范，并且在第一功能的规范内包括对应于内部子系统块的第二功能的规范。第一个函数的规范引用外部子系统块的参数，并指定第二个函数的调用。第二函数的规范规定了对应于内子系统块中的叶块的第三函数的调用。第一个函数的规范引用与参数对应的变量，该变量由第二或第三个函数引用。执行HLL程序实例化设计模型。

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