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    • 13. 发明申请
    • INTERACTIVE VIDEO SYSTEM
    • 互动视频系统
    • US20110145881A1
    • 2011-06-16
    • US12962529
    • 2010-12-07
    • Anthony HartmanGeorge Shaw
    • Anthony HartmanGeorge Shaw
    • H04N7/173
    • H04N21/4788H04N7/15H04N21/42203H04N21/4223H04N21/4438H04N21/4755
    • An interactive video system is provided that is capable of combining streaming televised events with video conferencing technology to create a social television experience. A first user is able to connect via a webcam and microphone to a server that combines the webcam video and sound from the microphone with a streaming video that could be a televised event. The combined webcam video, microphone sound, and streaming video is then broadcast to the first user and other users such that the users are capable of viewing the streaming video with the live conferencing video and sound from the first user. This procedure may be repeated such that a plurality of users may video conference live on top of the streaming video.
    • 提供了一种交互式视频系统,其能够将流媒体电视事件与视频会议技术相结合,以创建社交电视体验。 第一个用户能够通过网络摄像头和麦克风连接到将麦克风的网络摄像头视频和声音与可以是电视转播事件的流式视频相结合的服务器。 然后将组合的网络摄像头视频,麦克风声音和流视频广播到第一用户和其他用户,使得用户能够使用来自第一用户的现场会议视频和声音来观看流式视频。 可以重复该过程,使得多个用户可以在流式视频的顶部上进行视频会议。
    • 15. 发明申请
    • Using trap routines in a RISC microprocessor architecture
    • 在RISC微处理器架构中使用陷阱程序
    • US20080071991A1
    • 2008-03-20
    • US11981482
    • 2007-10-31
    • George ShawMartin McClurgBradley JensenRussell FishCharles Moore
    • George ShawMartin McClurgBradley JensenRussell FishCharles Moore
    • G06F12/08
    • G06F12/0875G06F9/30014G06F9/3005G06F9/30134G06F9/30145G06F9/30167G06F9/322G06F9/3824G06F9/3861G06F9/3877G06F9/3879G09G5/363G09G5/393G09G2360/121G09G2360/126
    • A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.
    • 微处理器以100 MHz内部时钟频率执行100个本机MIPS峰值性能。 中央处理单元(CPU)指令集是硬连线的,允许大多数指令在一个周期内执行。 “流通”设计允许下一条指令在先前指令完成之前启动,从而提高性能。 微处理单元(MPU)包含52个通用寄存器,包括16个全局数据寄存器,一个索引寄存器,一个计数寄存器,一个16深可寻址寄存器/返回堆栈以及一个18深操作数堆栈。 两个堆栈都包含顶部元素中的索引寄存器,缓存在芯片上,并在需要时自动溢出并从外部存储器中重新填充。 堆栈最小化数据移动,并在过程调用,参数传递和变量赋值期间最小化存储器访问。 此外,MPU还包含一个模式/状态寄存器和41个用于I / O,控制,配置和状态的本地寻址寄存器。 CPU包含高性能零操作数双堆栈架构MPU和执行指令传输数据,计数事件,测量时间和执行其他与时序相关的功能的输入输出处理器(IOP)。 零操作数堆栈架构消除了操作数位。 堆栈还可以在过程内和跨过程中最小化寄存器保存和加载,从而允许较短的指令序列和更快的运行代码。 指令简单易于解码和执行,允许MPU和IOP在单个时钟周期内发出和完成指令,每个时钟周期为100个本机MIPS峰值执行。 每次执行指令提取或预取时,CPU使用8位操作码,最多可从内存中获取四条指令。 这些指令可以重复,而不会从内存重新读取。 当直接连接到DRAM而没有高速缓存时,这将保持高性能。
    • 17. 发明授权
    • Abrasive and polishing sheets
    • 磨料和抛光片
    • US4437269A
    • 1984-03-20
    • US175586
    • 1980-08-05
    • George Shaw
    • George Shaw
    • A44B18/00B24D11/00B24D11/02
    • A44B18/00B24D11/00
    • An abrasive or polishing sheet has indicia carried on its rear face overlaid by a translucent textile material providing a surface engageable by hooks, the material being adhered to the said indicia and their information content remain discernible through the said material. The sheet can be secured to a hooked surface of a carrier unit and can be removed therefrom and reused. The grit size indication is provided without needing to print the fabric.The textile material is a brushed, knitted nylon having less than 20 loops or curls per square mm. A carrier pad has a material to which the sheet can be attached. The material of the pad has inclined stalks extending therefrom which have unhooked ends. These features result in a very low peel strength between sheet and pad.
    • 研磨片或抛光片的后表面上带有标示,该标记覆盖着半透明的纺织材料,其提供可通过钩接合的表面,该材料被粘附到所述标记上,并且其信息内容可以通过所述材料辨别。 片材可以固定到承载单元的钩形表面上,并且可以将其移除并重复使用。 提供砂粒尺寸指示,无需打印织物。 纺织材料是具有小于20圈或每平方毫米卷发的拉丝针织尼龙。 载体垫具有可附着片材的材料。 垫的材料具有从其延伸的倾斜茎具有未钩端。 这些特征导致片材和垫片之间的剥离强度非常低。