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11. 发明授权

US08488366B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08488366B2
公开(公告)日：2013-07-16
申请号：US13043681
申请日：2011-03-09
申请人： Tomonori Kurosawa , Takahiko Sasaki
发明人： Tomonori Kurosawa , Takahiko Sasaki
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/0035 , G11C13/0069 , G11C16/3418 , G11C2013/0083 , G11C2013/0092
摘要： A semiconductor memory device in accordance with an embodiment includes: a memory cell array having memory cells disposed at respective intersections of first lines and second lines; and a control circuit configured to apply a first pulse voltage multiple times to selected one of the first lines and selected one of the second lines, such that a certain potential difference is applied to a selected memory cell thereby causing transition of a resistance state. The control circuit is configured to, when the selected memory cell is not caused to undergo transition of the resistance state even after application of the first pulse voltage a certain number of times, execute a rescue operation where a second pulse voltage is applied to the selected memory cell subsequent to application of the first pulse voltage, the second pulse voltage having a pulse width longer than that of the first pulse voltage.
摘要翻译：根据实施例的半导体存储器件包括：存储单元阵列，其具有设置在第一线和第二线的相应交点处的存储单元; 以及控制电路，被配置为对选择的第一行和所选择的第二行之一多次施加第一脉冲电压，使得一定的电位差被施加到所选择的存储器单元，从而导致电阻状态的转变。控制电路被配置为，即使在施加了第一脉冲电压一定次数之后，所选择的存储单元也不会发生电阻状态的转变，则执行对所选择的第二脉冲电压施加第二脉冲电压的救援操作在施加第一脉冲电压之后，第二脉冲电压具有比第一脉冲电压的脉冲宽度更长的脉冲宽度。

12. 发明申请

US20110141794A1 SEMICONDUCTOR MEMORY DEVICE AND INSPECTING METHOD OF THE SAME 失效
标题翻译：半导体存储器件及其检测方法
公开(公告)号：US20110141794A1
公开(公告)日：2011-06-16
申请号：US12884694
申请日：2010-09-17
申请人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
发明人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
IPC分类号： G11C29/02 , G11C11/21
CPC分类号： G11C29/02 , G11C11/16 , G11C29/025 , G11C2029/1204
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells, a first decoder configured to select a first line as an inspection target from the lines, a second decoder configured to select a second line for generating a reference voltage from the lines, a driver configured to charge the first and second lines, a discharging circuit configured to simultaneously discharge the first and second lines, and a sense amplifier configured to compare a voltage of the first line with a voltage of the second line to detect a defect of the first line while the first line is discharged.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，其包括存储单元，提供用于对应于存储单元的线，第一解码器，被配置为从线选择第一行作为检查对象;第二解码器，被配置为选择用于从所述线路产生参考电压的第二线路，被配置为对所述第一和第二线路充电的驱动器，配置成同时对所述第一和第二线路进行放电的放电电路;以及读出放大器，被配置为将所述第一线路的电压与第一线的电压在第一线放电时检测第一线的缺陷。

13. 发明授权

US08139396B2 Resistance change memory and control method thereof 失效
标题翻译：电阻变化记忆及其控制方法
公开(公告)号：US08139396B2
公开(公告)日：2012-03-20
申请号：US12880642
申请日：2010-09-13
申请人： Tomonori Kurosawa , Hiroshi Maejima
发明人： Tomonori Kurosawa , Hiroshi Maejima
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C8/12 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C2213/71 , G11C2213/72
摘要： According to one embodiment, a resistance change memory includes a memory cell array in which a plurality of blocks are provided, resistance change storage elements which are provided in blocks and which store data in accordance with a change in resistance state, first and second wirings in the blocks, each of the first and second wirings being connected to each of resistance change storage elements, and a control circuit which controls the state of a selected block targeted for operation and the state of unselected blocks except the selected block among the blocks. The control circuit respectively applies first and second unselect potentials to the first and second wirings in at least one of the unselected blocks during a period in which the selected block is in operation.
摘要翻译：根据一个实施例，电阻变化存储器包括其中提供多个块的存储单元阵列，电阻变化存储元件，其设置在块中并且根据电阻状态的变化存储数据，第一和第二布线所述块，所述第一和第二布线中的每一个连接到每个电阻变化存储元件，以及控制电路，所述控制电路控制所选择的块的操作状态以及所述块之外的所选块以外的未选择块的状态。控制电路在所选择的块正在运行的时段期间分别在至少一个未选择的块中向第一和第二布线施加第一和第二未选择电位。

14. 发明申请

US20110255330A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110255330A1
公开(公告)日：2011-10-20
申请号：US13051614
申请日：2011-03-18
申请人： Takahiko SASAKI , Tomonori Kurosawa
发明人： Takahiko SASAKI , Tomonori Kurosawa
IPC分类号： G11C11/21
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0038 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , H01L27/1021
摘要： A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array configured by memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies to any one of the memory cells through the first and second lines a voltage necessary for an operation of any one of the memory cells. A current limiting circuit is connected to the first line and limits a current flowing across the memory cell during an operation to a certain limit value. During an operation, the control circuit supplies a first voltage to the first line while supplying to the second line a second voltage. The second voltage lowers over time.
摘要翻译：根据本发明的一个实施例的非易失性半导体存储器件包括由存储单元构成的存储单元阵列，每个存储单元分别设置在第一线路和第二线路之间，并且每个都包括可变电阻器。控制电路通过第一和第二线路应用于任何一个存储器单元，用于存储单元中的任何一个的操作所需的电压。电流限制电路连接到第一线，并且将在操作期间流过存储器单元的电流限制到某一极限值。在操作期间，控制电路向第一线路提供第一电压，同时向第二线路提供第二电压。第二个电压随着时间的推移而下降。

15. 发明授权

US08264867B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08264867B2
公开(公告)日：2012-09-11
申请号：US12885881
申请日：2010-09-20
申请人： Kazuaki Kawaguchi , Takahiko Sasaki , Tomonori Kurosawa
发明人： Kazuaki Kawaguchi , Takahiko Sasaki , Tomonori Kurosawa
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0061 , G11C2013/0083
摘要： According to one embodiment, a nonvolatile semiconductor storage device having a plurality of operation modes, includes: a plurality of first lines; a plurality of second lines; a plurality of memory cells; a first selection unit that charges the first line to a first selection voltage; and a second selection unit that charges a second line to an unselection voltage and discharges the second line to a second selection voltage after the first line is charged to the first selection voltage by the first selection unit, wherein the second selection unit adjusts at least one of a level of the second selection voltage to which the second line to be selected is to be discharged and a time constant when discharging the second line to be selected, in accordance with an operation mode in which the nonvolatile semiconductor storage device operates among the plurality of operation modes.
摘要翻译：根据一个实施例，具有多个操作模式的非易失性半导体存储装置包括：多个第一线; 多条第二线; 多个存储单元; 第一选择单元，将第一行充电到第一选择电压; 以及第二选择单元，其在第一线路被第一选择单元充电到第一选择电压之后，将第二线路充电到非选择电压并将第二线路放电到第二选择电压，其中第二选择单元调整至少一个根据非易失性半导体存储装置在多个操作中的操作模式，要选择要选择的第二线路的第二选择电压的电平和放电要选择的第二线路的时间常数的操作模式。

16. 发明授权

US08149638B2 Semiconductor memory device and inspecting method of the same 失效
标题翻译：半导体存储器件及其检测方法
公开(公告)号：US08149638B2
公开(公告)日：2012-04-03
申请号：US12884694
申请日：2010-09-17
申请人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
发明人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C11/16 , G11C29/025 , G11C2029/1204
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells, a first decoder configured to select a first line as an inspection target from the lines, a second decoder configured to select a second line for generating a reference voltage from the lines, a driver configured to charge the first and second lines, a discharging circuit configured to simultaneously discharge the first and second lines, and a sense amplifier configured to compare a voltage of the first line with a voltage of the second line to detect a defect of the first line while the first line is discharged.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，其包括存储单元，提供用于对应于存储单元的线，第一解码器，被配置为从线选择第一行作为检查对象;第二解码器，被配置为选择用于从所述线路产生参考电压的第二线路，被配置为对所述第一和第二线路充电的驱动器，配置成同时对所述第一和第二线路进行放电的放电电路;以及读出放大器，被配置为将所述第一线路的电压与第一线的电压在第一线放电时检测第一线的缺陷。

17. 发明申请

US20110235394A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110235394A1
公开(公告)日：2011-09-29
申请号：US13033151
申请日：2011-02-23
申请人： Takahiko Sasaki , Tomonori Kurosawa
发明人： Takahiko Sasaki , Tomonori Kurosawa
IPC分类号： G11C11/21
CPC分类号： G11C13/0069 , G11C13/0026 , G11C13/004 , G11C13/0064 , G11C2013/0083 , G11C2213/72
摘要： A control circuit applies a first voltage to selected one of first lines and applies a second voltage having a voltage value smaller than that of the first voltage to selected one of second lines, such that a certain potential difference is applied across a memory cell disposed at an intersection of the selected one of the first lines and the selected one of the second lines. A current limiting circuit sets a compliance current defining an upper limit of a cell current flowing in the memory cell, and controls such that the cell current flowing in the memory cell does not exceed the compliance current. The current limiting circuit comprises a current generating circuit and a first current mirror circuit. The current generating circuit generates a first current having a current value equal to a current value of the cell current at a certain timing multiplied by a certain constant. The first current mirror circuit mirrors the first current to a current path supplying the first voltage to the first lines.
摘要翻译：控制电路将第一电压施加到所选择的第一行中的一个，并将具有小于第一电压的电压值的第二电压施加到所选择的第二行中的一个，使得在设置在第二行的存储单元上施加一定的电位差所选择的第一行和所选择的第二行之一的交集。电流限制电路设定限定在存储单元中流动的电池电流的上限的顺从电流，并进行控制使得在存储单元中流动的电池电流不超过顺应性电流。限流电路包括电流产生电路和第一电流镜电路。电流产生电路产生具有等于电池电流当前值的电流值的第一电流，该电流值以某一定时乘以一定常数。第一电流镜电路将第一电流反射到向第一线提供第一电压的电流路径。

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