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    • 11. 发明授权
    • Semiconductor memory device with data error compensation
    • 具有数据误差补偿的半导体存储器件
    • US5398206A
    • 1995-03-14
    • US654379
    • 1991-02-12
    • Mitsuru AkizawaKazuhiko IwasakiKouki NoguchiRyuuji ShibataNoboru Yamaguchi
    • Mitsuru AkizawaKazuhiko IwasakiKouki NoguchiRyuuji ShibataNoboru Yamaguchi
    • G11C29/00G11C29/24G11C7/00G11C8/00
    • G11C29/808G11C29/24G11C29/74G11C29/76
    • A semiconductor memory device includes signal lines, a decoder for decoding an inputted address to output the decoded result to some of the signal lines, a matrixed memory array, a part of which being pre-specified as a compensated area, read out means for reading out data from memory cells in an area specified in accordance with a decode signal on the some signal line, a detector for detecting that the address is related with the compensated area from the decode signal on the some signal lines, the compensated area being pre-related with the some signal lines, and a fixed data outputting circuit for merging predetermined data into a predetermined part of the data read out from the memory cells in accordance with the detection signal to output the merged data. The fixed data outputting circuit is controlled by a control circuit in response to a merge control signal to output the data read out from the memory cells without the merging operation.
    • 半导体存储器件包括信号线,用于对输入的地址进行解码以将解码结果输出到某些信号线的解码器,其一部分被预先指定为补偿区域的矩阵存储器阵列,读出装置 在某些信号线上根据解码信号指定的区域中的存储器单元输出数据;检测器,用于检测所述地址与所述一些信号线上的解码信号中的所述补偿区域相关,所述补偿区域是预处理的, 与一些信号线相关联的固定数据输出电路,以及用于根据检测信号将预定数据合并到从存储器单元读出的数据的预定部分中以输出合并数据的固定数据输出电路。 固定数据输出电路由控制电路根据合并控制信号进行控制,以输出从存储单元读出的数据,而不进行合并操作。