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    • 12. 发明申请
    • Nanotube with a T shaped structure and a field effect transistor, and a method of manufacturing the same
    • 具有T形结构的纳米管和场效应晶体管及其制造方法
    • US20060265789A1
    • 2006-11-23
    • US11355135
    • 2006-02-16
    • Takazumi KawaiYoshiyuki Miyamoto
    • Takazumi KawaiYoshiyuki Miyamoto
    • H01L29/00
    • H01L51/0048B82Y10/00H01L51/0504H01L51/0508H01L51/0595
    • To realize a transistor with a channel and a gate, both being formed with nanotubes, by joining the nanotubes in the form of SP3 bonding, a substrate, on which a pair of source and drain electrodes 27, and a gate terminal 28 are formed, is prepared (Fig. (a)), and then a catalytic layer 20 is formed at the one of the source and drain electrodes 27 (Fig. (b)). A first CNT 23 is formed (Fig. (d)) between the pair of source and drain electrodes 27 by growing the CNT (Fig. (c)) in which the catalytic layer 20 is a core. A second CNT 24 is picked by a holding means 25, and after a cap is eliminated and an opening portion is cleaned using the electron beam as needed, the opening portion is contacted to the side of the first CNT 23, thereby joining the two CNT (fig. (e)). The other end portion of the second CNT 24 is positioned at the gate terminal 28 (Fig. (f)). End portions of the CNT are fixed on the electrodes and the terminal by selectively irradiating metallic ion.
    • 为了实现具有沟道和栅极的晶体管,均通过以纳米管形成的方式形成纳米管,通过以SP3键合的形式连接纳米管,形成有一对源极和漏极电极27以及栅极端子28的基板, (图(a)),然后在源极和漏极电极27(图(b))之一处形成催化剂层20。 通过生长催化剂层20为核心的CNT(图(c)),在一对源极和漏极电极27之间形成第一CNT 23(图(d))。 第二CNT24由保持装置25拾取,并且在消除盖并且根据需要使用电子束清洁开口部之后,开口部分与第一CNT 23的一侧接触,从而将两个CNT (图(e))。 第二CNT 24的另一端部位于栅极端子28(图(f))。 通过选择性地照射金属离子,将CNT的端部固定在电极和端子上。
    • 17. 发明授权
    • Fabrication method of semiconductor integrated circuit device
    • 半导体集成电路器件的制造方法
    • US06797442B2
    • 2004-09-28
    • US10614789
    • 2003-07-09
    • Kazuyuki TokorozukiTetsuji YokouchiYoshiyuki MiyamotoKoji Yamamoto
    • Kazuyuki TokorozukiTetsuji YokouchiYoshiyuki MiyamotoKoji Yamamoto
    • G03F900
    • G03F7/70558
    • An average value of dimensions of resist patterns formed each time exposure processing is effected on semiconductor substrates of a predetermined number of lots, is compared with a target dimension. When a drift between each of the dimensions of the formed resist patterns and the target dimension is larger than a first value, exposure energy is corrected with a relatively large correction value &agr;1. When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the first value and larger than a second value, exposure energy is corrected with a relatively small correction value &agr;2. When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the second value, no exposure energy is corrected. Exposure processing is effected on a semiconductor substrate of the next lot by using the calculated exposure energy.
    • 将在预定批次的半导体衬底上进行每次曝光处理形成的抗蚀剂图案的尺寸的平均值与目标尺寸进行比较。 当形成的抗蚀剂图案的每个尺寸和目标尺寸之间的漂移大于第一值时,以相对大的校正值α1校正曝光能量。 当形成的抗蚀剂图案的每个尺寸与目标尺寸之间的漂移小于第一值并且大于第二值时,以相对较小的校正值α2校正曝光能量。 当形成的抗蚀剂图案的每个尺寸和目标尺寸之间的漂移小于第二值时,不会校正曝光能量。 通过使用计算出的曝光能量对下一批次的半导体衬底进行曝光处理。