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11. 发明授权

US08865528B2 Thin film transistor substrate and the method thereof 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08865528B2
公开(公告)日：2014-10-21
申请号：US12844356
申请日：2010-07-27
申请人： Jean-Ho Song , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
发明人： Jean-Ho Song , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
摘要： A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要翻译：薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。栅极绝缘层可以具有台阶形状。

12. 发明申请

US20110133193A1 THIN FILM TRANSISTOR SUBSTRATE AND THE METHOD THEREOF 有权
标题翻译：薄膜晶体管基板及其方法
公开(公告)号：US20110133193A1
公开(公告)日：2011-06-09
申请号：US12844356
申请日：2010-07-27
申请人： Jean-Ho SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
发明人： Jean-Ho SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC分类号： H01L27/12 , H01L29/786 , H01L21/336
CPC分类号： H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
摘要： A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
摘要翻译：薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。栅极绝缘层可以具有台阶形状。

13. 发明授权

US08946004B2 Contact portion of wire and manufacturing method thereof 有权
标题翻译：电线接触部分及其制造方法
公开(公告)号：US08946004B2
公开(公告)日：2015-02-03
申请号：US12544144
申请日：2009-08-19
申请人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
发明人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
IPC分类号： H01L29/786 , H01L27/12 , G02F1/1362
CPC分类号： H01L24/05 , G02F1/136227 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L2224/04042 , H01L2924/14 , H01L2924/1426 , H01L2924/00
摘要： A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.
摘要翻译：公开了布线的接触部分及其制造方法。根据实施例的布线的接触部分包括：基板; 设置在所述基板上的导电层; 设置在所述导电层上并具有接触孔的层间绝缘层; 设置在所述导电层上并填充所述接触孔的金属层; 以及透明电极，设置在所述层间绝缘层上并连接到所述金属层，其中所述层间绝缘层包括下绝缘层和设置在所述下绝缘层上的上绝缘层，所述下绝缘层在所述接触孔处被底切，并且金属层填充在下绝缘层被切下的部分。

14. 发明授权

US08723179B2 Thin film transistor panel having an etch stopper on semiconductor 有权
标题翻译：薄膜晶体管板在半导体上具有蚀刻停止层
公开(公告)号：US08723179B2
公开(公告)日：2014-05-13
申请号：US12957743
申请日：2010-12-01
申请人： Pil-Sang Yun , Ki-Won Kim , Hye-Young Ryu , Woo-Geun Lee , Seung-Ha Choi , Jae-Hyoung Youn , Kyoung-Jae Chung , Young-Wook Lee , Je-Hun Lee , Kap-Soo Yoon , Do-Hyun Kim , Dong-Ju Yang , Young-Joo Choi
发明人： Pil-Sang Yun , Ki-Won Kim , Hye-Young Ryu , Woo-Geun Lee , Seung-Ha Choi , Jae-Hyoung Youn , Kyoung-Jae Chung , Young-Wook Lee , Je-Hun Lee , Kap-Soo Yoon , Do-Hyun Kim , Dong-Ju Yang , Young-Joo Choi
IPC分类号： H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/20
CPC分类号： H01L29/41733 , H01L21/44 , H01L21/441 , H01L21/465 , H01L21/475 , H01L21/47573 , H01L21/47635 , H01L27/1214 , H01L27/1225 , H01L27/127 , H01L27/1288 , H01L29/66969 , H01L29/78606 , H01L29/7869 , H01L29/78696
摘要： A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
摘要翻译：薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的在蚀刻停止器上。

15. 发明申请

US20100230679A1 CONTACT PORTION OF WIRE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：接线方式及其制造方法
公开(公告)号：US20100230679A1
公开(公告)日：2010-09-16
申请号：US12544144
申请日：2009-08-19
申请人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Snag-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
发明人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Snag-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
IPC分类号： H01L29/786 , H01L29/49 , H01L21/28 , H01L21/336
CPC分类号： H01L24/05 , G02F1/136227 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L2224/04042 , H01L2924/14 , H01L2924/1426 , H01L2924/00
摘要： A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.
摘要翻译：公开了布线的接触部分及其制造方法。根据实施例的布线的接触部分包括：基板; 设置在所述基板上的导电层; 设置在所述导电层上并具有接触孔的层间绝缘层; 设置在所述导电层上并填充所述接触孔的金属层; 以及设置在所述层间绝缘层上且与所述金属层连接的透明电极，其中所述层间绝缘层包括下绝缘层和设置在所述下绝缘层上的上绝缘层，所述下绝缘层在所述接触孔处被底切，并且金属层填充在下绝缘层被切下的部分。

16. 发明授权

US08476123B2 Method for manufacturing thin film transistor array panel 有权
标题翻译：制造薄膜晶体管阵列面板的方法
公开(公告)号：US08476123B2
公开(公告)日：2013-07-02
申请号：US13109686
申请日：2011-05-17
申请人： Dong-Ju Yang , Yu-Gwang Jeong , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi , Tae-Woo Kim
发明人： Dong-Ju Yang , Yu-Gwang Jeong , Jean-Ho Song , Ki-Yeup Lee , Shin-Il Choi , Tae-Woo Kim
IPC分类号： H01L21/84
CPC分类号： H01L27/1288 , H01L21/32138 , H01L27/1214 , H01L27/1255 , H01L29/458
摘要： A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SF6 or SF6/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.
摘要翻译：薄膜晶体管阵列板的制造方法包括：形成栅极线; 在栅极线上形成绝缘层; 第一和第二硅层第一和第二金属层; 形成具有第一和第二部分的光致抗蚀剂图案; 通过蚀刻第一和第二金属层来形成第一和第二金属图案; 用SF6或SF6 / He处理第一金属图案; 通过蚀刻第二和第一硅层形成硅和半导体图案; 去除光致抗蚀剂图案的第一部分; 通过湿法蚀刻第二金属图案形成数据线的上层; 通过蚀刻第一金属和非晶硅图案形成数据线的下层和欧姆接触; 在上层形成包括接触孔的钝化层; 以及在所述钝化层上形成像素电极。

17. 发明授权

US08450737B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08450737B2
公开(公告)日：2013-05-28
申请号：US12784376
申请日：2010-05-20
申请人： Shin-Il Choi , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
发明人： Shin-Il Choi , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
IPC分类号： H01L31/00
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.
摘要翻译：薄膜晶体管阵列面板包括：基板; 设置在基板上并包括铜（Cu）的信号线; 钝化层，设置在所述信号线上并具有暴露所述信号线的一部分的接触孔; 以及设置在所述钝化层上并通过所述接触孔连接到所述信号线的所述部分的导电层，其中所述钝化层包括包含不包含硫的有机绝缘体的有机钝化层，以及制造所述薄膜的方法晶体管防止在信号线上形成异物。

18. 发明申请

US20110089421A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110089421A1
公开(公告)日：2011-04-21
申请号：US12784376
申请日：2010-05-20
申请人： Shin-Il CHOI , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
发明人： Shin-Il CHOI , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
IPC分类号： H01L29/786 , H01L27/12 , H01L21/782
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.
摘要翻译：薄膜晶体管阵列面板包括：基板; 设置在基板上并包括铜（Cu）的信号线; 钝化层，设置在所述信号线上并具有暴露所述信号线的一部分的接触孔; 以及设置在所述钝化层上并通过所述接触孔连接到所述信号线的所述部分的导电层，其中所述钝化层包括包含不包含硫的有机绝缘体的有机钝化层，以及制造所述薄膜的方法晶体管防止在信号线上形成异物。

19. 发明申请

US20100051934A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20100051934A1
公开(公告)日：2010-03-04
申请号：US12504483
申请日：2009-07-16
申请人： Jong-Hyun Choung , Bong-Kyun Kim , Byeong-Jin Lee , Sun-Young Hong , Pil-Sang Yun , Hong-Sick Park , Dong-Ju Yang , Young-Joo Choi , Nam-Seok Suh
发明人： Jong-Hyun Choung , Bong-Kyun Kim , Byeong-Jin Lee , Sun-Young Hong , Pil-Sang Yun , Hong-Sick Park , Dong-Ju Yang , Young-Joo Choi , Nam-Seok Suh
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/124 , H01L27/1288
摘要： A thin film transistor array panel and a method of manufacturing the same are provided according to one or more embodiments. In an embodiment, a method includes: forming a gate line on an insulation substrate; stacking a gate insulating layer, an oxide semiconductor layer, a first barrier layer, and a first copper layer on the gate line; performing a photolithography process on the oxide semiconductor layer, the first barrier layer, and the first copper layer and forming a data line including a source electrode, a drain electrode, and an oxide semiconductor pattern; forming a passivation layer having the contact hole that exposes the drain electrode on the data line and the drain electrode; and forming a pixel electrode that is connected to the drain electrode through the contact hole on the passivation layer, wherein the forming of a data line, a drain electrode, and an oxide semiconductor pattern includes wet etching the first copper layer and then wet etching the first barrier layer and the oxide semiconductor layer.
摘要翻译：根据一个或多个实施例提供薄膜晶体管阵列面板及其制造方法。在一个实施例中，一种方法包括：在绝缘基板上形成栅极线; 在栅极线上堆叠栅极绝缘层，氧化物半导体层，第一势垒层和第一铜层; 在所述氧化物半导体层，所述第一阻挡层和所述第一铜层上进行光刻工艺，并形成包括源电极，漏电极和氧化物半导体图案的数据线; 形成具有使数据线和漏电极上的漏电极露出的接触孔的钝化层; 以及形成通过钝化层上的接触孔连接到漏电极的像素电极，其中数据线，漏电极和氧化物半导体图案的形成包括湿蚀刻第一铜层，然后湿蚀刻第一阻挡层和氧化物半导体层。

20. 发明授权

US08557621B2 Method for manufacturing thin film transistor array panel 有权
标题翻译：制造薄膜晶体管阵列面板的方法
公开(公告)号：US08557621B2
公开(公告)日：2013-10-15
申请号：US13157806
申请日：2011-06-10
申请人： Jong-Hyun Choung , Yang Ho Bae , Jean Ho Song , O Sung Seo , Sun-Young Hong , Hwa Yeul Oh , Bong-Kyun Kim , Nam Seok Suh , Dong-Ju Yang , Wang Woo Lee
发明人： Jong-Hyun Choung , Yang Ho Bae , Jean Ho Song , O Sung Seo , Sun-Young Hong , Hwa Yeul Oh , Bong-Kyun Kim , Nam Seok Suh , Dong-Ju Yang , Wang Woo Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/32134 , G02F1/136227 , H01L27/1288 , H01L29/41733
摘要： A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括：在栅绝缘层和栅极线上依次形成第一硅层，第二硅层，下金属层和上金属层; 在上金属层上形成第一膜图案; 通过蚀刻上金属层和下金属层，形成第一下金属图案和包括突起的第一上金属图案; 通过蚀刻第一和第二硅层形成第一和第二硅图案; 通过灰化第一膜图案形成第二膜图案; 通过蚀刻第一上金属图案形成第二上金属图案; 通过蚀刻第一下金属图案和第一和第二硅图案来形成数据线和薄膜晶体管; 并在所得物上形成钝化层和像素电极。

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