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11. 发明授权

US06204204B1 Method and apparatus for depositing tantalum-based thin films with organmetallic precursor 失效
标题翻译：用有机金属前体沉积钽基薄膜的方法和设备
公开(公告)号：US06204204B1
公开(公告)日：2001-03-20
申请号：US09282952
申请日：1999-04-01
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
IPC分类号： H01L21302
CPC分类号： H01L21/76862 , C23C16/34 , C23C16/448 , H01L21/28556 , H01L21/76843
摘要： A method and apparatus are disclosed for depositing a tantalum-containing diffusion barrier, such as a TaN barrier layer, by dissolving a tantalum-bearing organometallic precursor, such as PEMAT or PDEAT, in an inert, low viscosity, high molecular weight, low volatility solvent, such as octane, heptane, decane or toluene. The precursor-solvent solution is vaporized and flowed over a substrate to deposit the barrier. The precursor solution has a viscosity substantially similar to that of the solvent by maintaining the ratio of precursor to solvent at a generally low value, such as approximately 10% precursor. The boiling point of the solvent is substantially similar to the boiling point of the precursor, such as within 50% of the precursor boiling point at one atmosphere, to enhance repeatability of barrier film quality. Resistivity of the barrier film is reduced by flowing a reactive gas with the precursor flow, the reactive gas reducing the carbon content of the barrier film, or by co-deposition of a resistivity-lowering metallic dopant with the precursor solution. Alternatively, resistivity is reduced by controlling the nitrogen content of the film by a post-deposition plasma treatment of the barrier with a reducing gas.
摘要翻译：公开了一种方法和装置，用于通过将含钽的有机金属前体如PEMAT或PDEAT溶解在惰性，低粘度，高分子量，低挥发性中来沉积含钽的扩散阻挡层，例如TaN阻挡层溶剂，如辛烷，庚烷，癸烷或甲苯。前体溶剂溶液蒸发并流过基底以沉积屏障。通过将前体与溶剂的比例保持在通常较低的值，例如约10％的前体，前体溶液具有与溶剂基本相似的粘度。溶剂的沸点基本上类似于前体的沸点，例如在一个大气压下的前体沸点的50％以内，以提高阻挡膜质量的重复性。阻挡膜的电阻率通过使与前体流反应的气体流动，反应气体降低阻挡膜的碳含量，或通过与前体溶液共沉积电阻率降低金属掺杂剂来降低。或者，通过用还原气体对阻挡层进行后期等离子体处理来控制膜的氮含量来降低电阻率。

12. 发明授权

US06471830B1 Inductively-coupled-plasma ionized physical-vapor deposition apparatus, method and system 失效
标题翻译：电感耦合等离子体离子化物理气相沉积装置，方法和系统
公开(公告)号：US06471830B1
公开(公告)日：2002-10-29
申请号：US09678267
申请日：2000-10-03
申请人： Mehrdad M. Moslehi , Ajit P. Paranjpe
发明人： Mehrdad M. Moslehi , Ajit P. Paranjpe
IPC分类号： C23C1434
CPC分类号： H01J37/321 , C23C14/358 , H01J37/32568
摘要： A system and related method are disclosed for performing an inductively-coupled-plasma ionized physical-vapor deposition (“PVD”) process for depositing material layers onto a substrate. Within a PVD process chamber are contained a target/cathode assembly, a chuck assembly, a process medium, a variable height inductively-coupled (“VHIC”) ionization coil segment and an antenna actuator for controlling the relative vertical position of the variable height inductively-coupled ionization coil segment. The VHIC coil segment can be contained within a dielectric liner and can be covered by a multi-slotted grounded electrostatic shield. The VHIC ionization coil segment can comprise one or more zones comprised of one or more coil loops powered by one or more radio-frequency power supplies. Each zone can be powered through an adjustable passive electrical component for providing multiple inductive zone operations during a deposition process.
摘要翻译：公开了一种系统和相关方法，用于执行用于将材料层沉积到衬底上的电感耦合等离子体离子化物理气相沉积（“PVD”）工艺。在PVD处理室内装有目标/阴极组件，卡盘组件，处理介质，可变高度感应耦合（“VHIC”）电离线圈段和用于控制可变高度感应的相对垂直位置的天线致动器耦合电离线圈段。 VHIC线圈段可以包含在电介质衬垫内，并且可以被多槽接地静电屏蔽覆盖。 VHIC电离线圈段可以包括由一个或多个由一个或多个射频电源供电的线圈环组成的一个或多个区域。每个区域可以通过可调节的无源电气部件供电，以在沉积过程中提供多个感应区域操作。

13. 发明授权

US06461675B2 Method for forming a copper film on a substrate 失效
标题翻译：在基板上形成铜膜的方法
公开(公告)号：US06461675B2
公开(公告)日：2002-10-08
申请号：US09113852
申请日：1998-07-10
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , Zeming Liu , Guihua Shang
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , Zeming Liu , Guihua Shang
IPC分类号： C23C1606
CPC分类号： H01L21/76858 , C23C16/0209 , C23C16/0245 , C23C16/0281 , C23C16/18 , H01L21/76843 , H01L21/76862 , H01L21/76876 , H01L21/76877 , H01L2221/1089
摘要： Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput. Alternatively, the adhesion promotion techniques can avoid the formation of an interface by graduated deposition of a first material and copper.
摘要翻译：通过粘合促进技术增强铜膜如铜互连对衬底底层（例如衬底扩散阻挡层）的粘合性。粘合促进技术可以修复铜膜和基材的界面，以增强铜膜的粘附性，从而高收率地形成嵌入的铜金属线和插塞。例如，种子层（包括铜籽晶层，合金种子层或反应物种子层）的热退火可以修复种子层和基底的界面处的污染。或者，粘合促进技术可以避免通过沉积惰性种子层（例如贵金属（例如铂）或钝化金属种子层）或通过在限制界面的污染最小化的预定条件下沉积籽晶层来污染界面，然后在允许生产量最大化的预定条件下沉积大块铜层。或者，粘合促进技术可以避免通过第一材料和铜的分级沉积形成界面。

14. 发明授权

US06294836B1 Semiconductor chip interconnect barrier material and fabrication method 失效
标题翻译：半导体芯片互连屏障材料及制造方法
公开(公告)号：US06294836B1
公开(公告)日：2001-09-25
申请号：US09219147
申请日：1998-12-22
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and tin. The barrier can comprise a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization in one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
摘要翻译：微电子半导体互连结构屏障和沉积方法为高性能器件互连提供改进的导电阻挡材料性质。阻挡层包括选自铂，钯，铱，铑和锡的掺杂剂。阻挡层可以包括选自钽，钨钛，铬和钴的难熔金属，并且还可以包括选自碳，氧和氮的第三元素。通过化学气相沉积可以通过化学气相沉积来沉积掺杂剂和其它阻挡材料以实现良好的阶梯覆盖，并且在一个实施例中，具有良好成核表面的相对适形的薄膜用于随后的金属化，例如铜金属化，屏障抑制铜扩散到其它层的器件，包括金属间电介质，预金属电介质和晶体管结构。

15. 发明授权

US5591493A Structure and method for incorporating an inductively coupled plasma source in a plasma processing chamber 失效
标题翻译：在等离子体处理室中结合电感耦合等离子体源的结构和方法
公开(公告)号：US5591493A
公开(公告)日：1997-01-07
申请号：US472606
申请日：1995-06-07
申请人： Ajit P. Paranjpe , Cecil J. Davis , Robert T. Matthews
发明人： Ajit P. Paranjpe , Cecil J. Davis , Robert T. Matthews
IPC分类号： C23C16/50 , C23F4/00 , H01J37/32 , H01L21/205 , H01L21/302 , H01L21/3065 , H05H1/46 , C23C16/00
CPC分类号： H01J37/321 , H05H1/46
摘要： A plasma processing chamber 10 having an inductively coupled plasma (ICP) source 12 mounted therein. The ICP source 12 comprises an antenna 14 encapsulated in epoxy 16 and surrounded by housing 18. The antenna 14 and epoxy 16 are hermetically sealed from plasma formation region 30. The antenna 14 is powered by at least one RF power supply 40 through at least one RF matching network 42. Dielectric capping plate 28 separates ICP source 12 from the plasma formation region 30 and may have a plurality of holes therein to provide a uniform showerhead distribution of process gases.
摘要翻译：具有安装在其中的感应耦合等离子体（ICP）源12的等离子体处理室10。 ICP源12包括封装在环氧树脂16中并被壳体18包围的天线14.天线14和环氧树脂16与等离子体形成区域30气密密封。天线14由至少一个RF电源40通过至少一个 RF匹配网络42.介电封盖板28将ICP源12与等离子体形成区域30分离，并且可以在其中具有多个孔以提供工艺气体均匀的喷头分布。

16. 发明授权

US5580385A Structure and method for incorporating an inductively coupled plasma source in a plasma processing chamber 失效
标题翻译：在等离子体处理室中结合电感耦合等离子体源的结构和方法
公开(公告)号：US5580385A
公开(公告)日：1996-12-03
申请号：US269414
申请日：1994-06-30
申请人： Ajit P. Paranjpe , Cecil J. Davis , Robert T. Matthews
发明人： Ajit P. Paranjpe , Cecil J. Davis , Robert T. Matthews
IPC分类号： C23C16/50 , C23F4/00 , H01J37/32 , H01L21/205 , H01L21/302 , H01L21/3065 , H05H1/46 , C23C16/00
CPC分类号： H01J37/321 , H05H1/46
摘要： A plasma processing chamber 10 having an inductively coupled plasma (ICP) source 12 mounted therein. The ICP source 12 comprises an antenna 14 encapsulated in epoxy 16 and surrounded by housing 18. The antenna 14 and epoxy 16 are hermetically sealed from plasma formation region 30. The antenna 14 is powered by at least one RF power supply 40 through at least one RF matching network 42. Dielectric capping plate 28 separates ICP source 12 from the plasma formation region 30 and may have a plurality of holes therein to provide a uniform showerhead distribution of process gases.
摘要翻译：具有安装在其中的感应耦合等离子体（ICP）源12的等离子体处理室10。 ICP源12包括封装在环氧树脂16中并被壳体18包围的天线14.天线14和环氧树脂16与等离子体形成区域30气密密封。天线14由至少一个RF电源40通过至少一个 RF匹配网络42.介电封盖板28将ICP源12与等离子体形成区域30分离，并且可以在其中具有多个孔以提供工艺气体均匀的喷头分布。

17. 发明授权

US5434107A Method for planarization 失效
标题翻译：平面化方法
公开(公告)号：US5434107A
公开(公告)日：1995-07-18
申请号：US188498
申请日：1994-01-28
申请人： Ajit P. Paranjpe
发明人： Ajit P. Paranjpe
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/463
CPC分类号： B29C43/003 , H01L21/31051 , B29C2043/025
摘要： A method for planarization of the upper surface of a semiconductor wafer. A wafer with features formed thereon is loaded into the apparatus after having been coated with an interlevel dielectric. Thereafter, the wafer is subjected to suitably elevated temperature while a uniform elevated pressure is applied. Once the temperature and pressure conditions exceed the yield stress of the film, the film will flow and fill the microscopic as well as global depressions in the wafer surface. Thereafter, the temperature and pressure is reduced so that the film will become firm again thereby leaving a planar upper surface on the wafer.
摘要翻译：一种半导体晶片的上表面的平坦化方法。具有形成在其上的特征的晶片在已经涂覆有层间电介质之后被装载到设备中。此后，在施加均匀的升高的压力的同时使晶片经受适当的升高的温度。一旦温度和压力条件超过膜的屈服应力，膜将流动并填充晶片表面的微观以及全局凹陷。此后，降低温度和压力，使得膜再次变得牢固，从而在晶片上留下平坦的上表面。

18. 发明授权

US5249865A Interferometric temperature measurement system and method 失效
标题翻译：干涉测温系统及方法
公开(公告)号：US5249865A
公开(公告)日：1993-10-05
申请号：US874658
申请日：1992-04-27
申请人： Ajit P. Paranjpe , Steven A. Henck , Walter M. Duncan
发明人： Ajit P. Paranjpe , Steven A. Henck , Walter M. Duncan
IPC分类号： G01K11/00 , G01J5/58
CPC分类号： G01J5/58 , G01J5/0003 , G01J5/0007 , G01K11/00
摘要： An interferonmetric temperature measurement system is described for determining the temperature of a sample. The system comprises three detectors for measuring various intensities of a beam of electromagnetic radiation reflected off the sample and circuitry for determining the temperature from the intensities. The detectors measure the intensity of the beam and two orthogonally polarized components of the beam.
摘要翻译：描述了用于确定样品的温度的干涉测量温度测量系统。该系统包括三个检测器，用于测量样品反射的电磁辐射束的各种强度和用于根据强度确定温度的电路。检测器测量光束的强度和光束的两个正交极化分量。

19. 发明授权

US07037574B2 Atomic layer deposition for fabricating thin films 失效
标题翻译：用于制造薄膜的原子层沉积
公开(公告)号：US07037574B2
公开(公告)日：2006-05-02
申请号：US09864714
申请日：2001-05-23
申请人： Ajit P. Paranjpe , Sanjay Gopinath , Thomas R. Omstead , Randhir S. Bubber , Ming Mao
发明人： Ajit P. Paranjpe , Sanjay Gopinath , Thomas R. Omstead , Randhir S. Bubber , Ming Mao
IPC分类号： H01L21/8242 , H01L21/336 , C30B23/00 , C30B25/00
CPC分类号： H01L21/0228 , B82Y10/00 , B82Y25/00 , B82Y40/00 , C23C16/403 , C23C16/45527 , C23C16/56 , G11B5/3109 , G11B5/3163 , G11B5/3909 , G11B5/3967 , G11B2005/3996 , H01F41/307 , H01L21/02178 , H01L21/02205 , H01L21/0234 , H01L21/3162 , Y10T428/24843
摘要： An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (Ra˜2 Å), pure (impurities
摘要翻译：原子层沉积（ALD）工艺通过等离子体退火在不同的膜厚度上沉积微电子结构的薄膜，例如先进的间隙和隧道结应用，以获得所需的本征膜应力和击穿膜强度。 ALD工艺的主要优点是接近100％的阶梯覆盖，其侧壁均匀分布。该方法提供了具有改进的击穿强度（9-10MV / cm）的平滑的（R a aα2），纯的（杂质<1 AT。％），ALO x ）具有商业上可行的吞吐量。

20. 发明授权

US5888899A Method for copper doping of aluminum films 失效
标题翻译：铝膜铜掺杂方法
公开(公告)号：US5888899A
公开(公告)日：1999-03-30
申请号：US829885
申请日：1997-04-02
申请人： Ajit P. Paranjpe
发明人： Ajit P. Paranjpe
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76877 , H01L23/53219 , H01L2924/0002
摘要： An embodiment of the instant invention is a method of forming a conductive structure over a semiconductor wafer, the method comprising the steps of: forming a first aluminum layer (14, 24) of a thickness; forming a conductive layer (18,28) of a material which is not readily etched by aluminum-etching etchants on the first aluminum layer, the conuctive layer having a thickness; forming a second aluminum layer (20, 30) on the conductive layer, the second aluminum layer having a thickness; patterning and etching the second aluminum layer thereby exposing a portion of the conductive layer; etching the exposed portion of the conductive layer thereby exposing a portion of the first aluminum layer; etching the exposed portion of the first aluminum layer; subjecting semiconductor wafer to a thermal step thereby diffusing the material in the conductive layer from the conductive layer into the first and second aluminum layers; and wherein the thickness of the conductive layer is much thinner than the thicknesses of the first and second aluminum layers. A plurality of aluminum/conductive/aluminum layers may be formed prior to patterning and etching. Preferably, the material of the conductive layer is comprised of: copper, scandium, tantalum, or vanadium, and the conductive layer is approximately 10 to 30 .ANG. thick and comprised of copper. More preferably, the copper layer is approximately 20 .ANG. thick. Preferably, the first aluminum layer is approximately 1500 to 3000 .ANG. thick, and the second aluminum layer is approximately 1500 to 3000 .ANG. thick.
摘要翻译：本发明的一个实施例是在半导体晶片上形成导电结构的方法，该方法包括以下步骤：形成厚度的第一铝层（14,24）; 在所述第一铝层上形成不易被铝蚀刻蚀刻剂蚀刻的材料的导电层（18,28），所述导电层具有厚度; 在所述导电层上形成第二铝层（20,30），所述第二铝层具有厚度; 图案化和蚀刻第二铝层，从而暴露导电层的一部分; 蚀刻导电层的暴露部分，从而暴露第一铝层的一部分; 蚀刻第一铝层的暴露部分; 使半导体晶片经受热步骤，从而将导电层中的材料从导电层扩散到第一和第二铝层中; 并且其中所述导电层的厚度比所述第一和第二铝层的厚度薄得多。可以在图案化和蚀刻之前形成多个铝/导电/铝层。优选地，导电层的材料包括：铜，钪，钽或钒，并且导电层厚度约为10至30埃，由铜构成。更优选地，铜层的厚度约为20。优选地，第一铝层的厚度约为1500至3000，第二铝层的厚度约为1500至3000。

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