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11. 发明申请

US20070030739A1 Method of comparison between cache and data register for non-volatile memory 有权
标题翻译：用于非易失性存储器的缓存和数据寄存器之间的比较方法
公开(公告)号：US20070030739A1
公开(公告)日：2007-02-08
申请号：US11580660
申请日：2006-10-13
申请人： Hendrik Hartono , Benjamin Louie , Aaron Yip , Hagop Nazarian
发明人： Hendrik Hartono , Benjamin Louie , Aaron Yip , Hagop Nazarian
IPC分类号： G11C7/06
CPC分类号： G11C7/22 , G06F12/0893 , G11C16/3436 , G11C2207/2245 , G11C2216/14
摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.
摘要翻译：描述了一种非易失性存储器件和数据比较电路，其有助于比较诸如存储器的I / O缓冲器或数据高速缓冲存储器和读出放大器的两个数据块之间的数据，其允许简单和快速地比较数据位并产生指示数据匹配或不匹配的信号标志。这允许一个简单的并行数据位比较功能，允许快速的初始比较结果，而不需要耗时的单独的逐位数据比较。在一个实施例中，要比较的两个数据块被分成多个成对段，其中每对段被数据比较电路并行地比较，使得可以将错误匹配定位到受影响的数据段或结果逻辑组合以指示完整数据块的匹配或不匹配。

12. 发明申请

US20050105327A1 Serial transistor-cell array architecture 有权
标题翻译：串行晶体管单元阵列架构
公开(公告)号：US20050105327A1
公开(公告)日：2005-05-19
申请号：US10699652
申请日：2003-11-04
申请人： Hagop Nazarian
发明人： Hagop Nazarian
IPC分类号： G11C11/00 , G11C11/16 , G11C13/00 , G11C13/02 , G11C16/02 , G11C16/26 , G11C27/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/16 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2213/78 , G11C2213/79
摘要： A memory array architecture suitable for variable resistance memory that mitigates sneak path and associated problems by limiting the number of memory cells associated with an addressed cell to a known number having a sneak path resistance that can be calculated and taken into consideration when sensing the addressed memory cell. Blocks of memory cells are associated with access transistors, which separate the memory cells connected thereto into one half (½) sections of cell blocks. The access transistors can be associated with n memory cells, where n is an even number of at least 2; there may or may not be an equal number of cells on either side of the transistor. The memory array has memory cells, which are grouped into 1T-2nCell blocks.
摘要翻译：一种适用于可变电阻存储器的存储器阵列架构，其通过将与所寻址的单元相关联的存储器单元的数量限制为具有潜行路径电阻的已知数量来减轻潜行路径和相关问题，所述已知数量可以在感测所寻址的存储器时被计算和考虑细胞。存储器单元的块与存取晶体管相关联，存取晶体管将连接到其的存储单元分成单元块的一半（1/2）段。存取晶体管可以与n个存储器单元相关联，其中n是至少2的偶数; 在晶体管的任一侧上可能有也可能没有相同数量的单元。存储器阵列具有存储单元，其被分组为1T-2nCell块。

13. 发明授权

US08520437B2 High read speed memory with gate isolation 有权
标题翻译：具有门隔离的高速读存储器
公开(公告)号：US08520437B2
公开(公告)日：2013-08-27
申请号：US13600527
申请日：2012-08-31
申请人： Richard Fastow , Hagop Nazarian , Lei Xue
发明人： Richard Fastow , Hagop Nazarian , Lei Xue
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06
CPC分类号： G11C16/0483 , G11C5/063 , H01L27/0207 , H01L27/11529 , H01L27/11573
摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.
摘要翻译：本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

14. 发明申请

US20130027081A1 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 有权
标题翻译：现场可编程门阵列使用两端非易失性存储器
公开(公告)号：US20130027081A1
公开(公告)日：2013-01-31
申请号：US13194500
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/0944 , H03K19/177
CPC分类号： H03K19/0013 , G11C13/0002 , G11C13/004 , G11C13/0069 , H03K19/0944 , H03K19/1776 , H03K19/17764 , H03K19/17776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.
摘要翻译：本文描述了利用电阻随机存取存储器（RRAM）技术提供现场可编程门阵列（FPGA）。作为示例，FPGA可以包括具有由垂直信号输出线交叉的并行信号输入线的开关块互连。可以在信号输入线和信号输出线的各个交叉处形成RRAM存储器单元。 RRAM存储器单元可以包括分压器，该分压器包括跨FPGA的VCC和VSS串联电串联的多个可编程电阻元件。分压器的公共节点驱动配置为激活或去激活交叉的通路晶体管的栅极。所公开的RRAM存储器可以提供高晶体管密度，高逻辑利用率，快速的编程速度，辐射抗扰度，快速上电和对FPGA技术的显着益处。

15. 发明申请

US20130027079A1 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 有权
公开(公告)号：US20130027079A1
公开(公告)日：2013-01-31
申请号：US13194479
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/177 , G11C11/00 , H01L21/82
CPC分类号： H03K19/17776 , G11C13/0021 , H01L27/101 , H03K19/0013 , H03K19/00315 , H03K19/0944 , H03K19/1776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

16. 发明授权

US08315079B2 Circuit for concurrent read operation and method therefor 有权
标题翻译：并行读取操作电路及其方法
公开(公告)号：US08315079B2
公开(公告)日：2012-11-20
申请号：US12900232
申请日：2010-10-07
申请人： Harry Kuo , Hagop Nazarian
发明人： Harry Kuo , Hagop Nazarian
IPC分类号： G11C7/06
CPC分类号： G11C13/0004 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C2207/005 , G11C2213/15 , G11C2213/78
摘要： A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.
摘要翻译：非易失性存储器件包括存储单元阵列，每个存储器单元具有电阻存储器单元和本地字线。每个存储单元具有第一端和第二端，第二端耦合到相应存储单元的本地字线。提供位线，每一个都连接到每个电阻存储器单元的第一端。提供了多个选择晶体管，每个选择晶体管与一个存储器单元相关联并且具有耦合到相关联的存储器单元的本地字线的漏极端子。提供第一和第二全局字线，每个字线耦合到至少一个选择晶体管的控制端。提供第一和第二源极线，每个耦合到至少一个选择晶体管的源极端子。存储器件被配置为在读取操作中同时读出一个选择的存储器单元中的所有电阻存储器单元。

17. 发明授权

US08274812B2 Write and erase scheme for resistive memory device 有权
标题翻译：电阻式存储器件的写入和擦除方案
公开(公告)号：US08274812B2
公开(公告)日：2012-09-25
申请号：US12815369
申请日：2010-06-14
申请人： Hagop Nazarian , Sung Hyun Jo
发明人： Hagop Nazarian , Sung Hyun Jo
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/15 , G11C2213/33
摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
摘要翻译：一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

18. 发明授权

US07894267B2 Deterministic programming algorithm that provides tighter cell distributions with a reduced number of programming pulses 有权
标题翻译：确定性编程算法，提供更小的单元分布，减少编程脉冲数
公开(公告)号：US07894267B2
公开(公告)日：2011-02-22
申请号：US11929741
申请日：2007-10-30
申请人： Hagop Nazarian , Michael Achter , Harry Kuo
发明人： Hagop Nazarian , Michael Achter , Harry Kuo
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/12
摘要： Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.
摘要翻译：改进存储器件编程的系统和方法。脉冲分量将不同的编程脉冲施加到存储单元。分析组件根据应用的不同编程脉冲测量存储器单元的一个或多个特性的值。计算组件根据存储单元的一个或多个特性的测量值来计算应用的不同编程脉冲。分析组件测量存储器单元的一个或多个特性的一个或多个值，计算组件根据存储器单元的一个或多个特性的一个或多个测量值来计算一个或多个编程脉冲，以及脉冲分量将一个或多个编程脉冲施加到存储器单元。

19. 发明授权

US07835189B2 High accuracy adaptive programming 有权
标题翻译：高精度自适应编程
公开(公告)号：US07835189B2
公开(公告)日：2010-11-16
申请号：US11687492
申请日：2007-03-16
申请人： Michael Achter , Hagop Nazarian
发明人： Michael Achter , Hagop Nazarian
IPC分类号： G11C16/06
CPC分类号： G11C16/10
摘要： Flash memory devices have a plurality of memory cells that can be erased and programmed. Performing a voltage verification check allows a for an appropriate state-change voltage to be applied to the flash memory device. The appropriate state-change voltage is determined though accessing a look-up table. Using an appropriate state-change voltage allows a cell to operate with more overall programming cycles.
摘要翻译：闪存设备具有可被擦除和编程的多个存储器单元。执行电压验证检查允许将适当的状态变化电压施加到闪存器件。通过访问查找表来确定适当的状态变化电压。使用适当的状态变化电压允许电池在更多的总体编程周期下运行。

20. 发明申请

US20100122146A1 ERROR CORRECTION FOR FLASH MEMORY 有权
标题翻译： FLASH存储器的错误校正
公开(公告)号：US20100122146A1
公开(公告)日：2010-05-13
申请号：US12267017
申请日：2008-11-07
申请人： Hagop Nazarian , Ping Hou
发明人： Hagop Nazarian , Ping Hou
IPC分类号： G11C29/52 , G06F11/00
CPC分类号： G06F11/1072 , G11C2029/0411
摘要： Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.
摘要翻译：本文描述了提供电子存储器的单位和多位纠错。作为示例，可以通过在一组分析的存储器单元的位级分布之间建立可疑区域来实现纠错。可疑区域可以定义分布的潜在错误位。如果对于分布检测到位错误，则可以首先将错误校正应用于可疑区域中的潜在错误位。通过识别怀疑的错误位并将初始误差修正限制在这种识别的位上，可以减轻或避免对分布的所有位应用纠错所涉及的复杂性，从而提高电子存储器误码校正的效率。

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