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    • 13. 发明授权
    • Power amplifier and chip carrier
    • 功率放大器和芯片载体
    • US5955926A
    • 1999-09-21
    • US942980
    • 1997-10-02
    • Hisanori UdaShigeyuki Okamoto
    • Hisanori UdaShigeyuki Okamoto
    • H03F3/60H03F3/68H03F3/04
    • H03F3/604H01L2224/49175H01L2924/19107
    • A plurality of FETs have their respective gates connected to each other through a first line and their respective drains connected to each other through a second line. A gate bias is applied to the gate of each FET through the first line and a drain bias is applied to the drain of each FET through the second line. A first matching circuit includes first capacitors connected to the signal path, inductors each connected between one end of each first capacitor and the ground potential, and second capacitors each connected between the other end of each first capacitor and the ground potential. The second matching circuit includes first capacitors each connected to the signal path, second capacitors each connected between one end of each first capacitor and the ground potential, and inductors each connected between the other end of each first capacitor and the ground potential.
    • 多个FET的各自的栅极通过第一线彼此连接,并且它们各自的漏极通过第二线彼此连接。 栅极偏置通过第一线施加到每个FET的栅极,并且通过第二线将漏极偏压施加到每个FET的漏极。 第一匹配电路包括连接到信号路径的第一电容器,每个连接在每个第一电容器的一端和接地电位之间的电感器,以及每个连接在每个第一电容器的另一端和地电位之间的第二电容器。 第二匹配电路包括每个连接到信号路径的第一电容器,每个连接在每个第一电容器的一端和接地电位之间的第二电容器,以及各自连接在每个第一电容器的另一端和地电位之间的电感器。