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11. 发明申请

US20050121802A1 Offset-bonded, multi-chip semiconductor device 失效
标题翻译：偏移式多芯片半导体器件
公开(公告)号：US20050121802A1
公开(公告)日：2005-06-09
申请号：US10995491
申请日：2004-11-24
申请人： Masaya Kawano , Satoshi Matsui
发明人： Masaya Kawano , Satoshi Matsui
IPC分类号： H01L25/18 , H01L23/50 , H01L25/00 , H01L25/065 , H01L25/07 , H01L29/40
CPC分类号： H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06555 , H01L2225/06562 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： The present invention is aimed at bonding a lower chip and an upper chip through bumps in a highly reliable manner, while ensuring a sufficient area for an external connection terminal region, by offsetting the upper chip to the lower chip. The substrate 2 has bumps 1 arranged on one surface thereof, and has a first chip 3 mounted on the other surface thereof. A second chip 4 is bonded to the first chip 3 through bumps 5, 6 while offsetting the second chip 4 to the first chip 3 in parallel. In the bonded state of the first chip 3 and the second chip 4, a part of the first chip 3 and a part of the second chip 4 are overlapped without aligning the centers of the both. The center of gravity of the second chip 4 falls inside a region surrounded by the outermost bumps between the first chip 3 and the second chip 4.
摘要翻译：本发明的目的在于通过将上芯片与下芯片相抵消，以高可靠性的方式将下芯片和上芯片焊接在一起，同时确保足够的外部连接端子区域。基板2在其一个表面上具有凸块1，并且具有安装在其另一个表面上的第一芯片3。第二芯片4通过凸块5,6接合到第一芯片3，同时平行地将第二芯片4与第一芯片3抵消。在第一芯片3和第二芯片4的接合状态下，第一芯片3的一部分和第二芯片4的一部分重叠而不对准两者的中心。第二芯片4的重心落在由第一芯片3和第二芯片4之间的最外侧的凸块包围的区域内。

12. 发明授权

US07768133B2 Semiconductor device and semiconductor module employing thereof 有权
标题翻译：半导体装置及其半导体模块
公开(公告)号：US07768133B2
公开(公告)日：2010-08-03
申请号：US11167162
申请日：2005-06-28
申请人： Satoshi Matsui , Masaya Kawano
发明人： Satoshi Matsui , Masaya Kawano
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/585 , H01L24/05 , H01L2224/0401 , H01L2224/05009 , H01L2224/05551 , H01L2224/05552 , H01L2224/05553 , H01L2224/05555 , H01L2224/13025 , H01L2224/14181 , H01L2224/16 , H01L2224/16146 , H01L2224/16225 , H01L2225/06513
摘要： A semiconductor device is provided with a silicon substrate and a structure filled in a through hole that has a rectangular cross section and extends through the silicon substrate. The structure comprises a pipe-shaped through electrode, stripe-shaped through electrodes, silicons, a first insulating film, a second insulating film and a third insulating film. The pipe-shaped through electrode is utilized as a pipe-shaped electric conductor that extends through the silicon substrate. In addition, the stripe-shaped through electrodes are provided in the interior of the pipe-shaped through electrode so that the stripe-shaped through electrodes extend through the silicon substrate and is spaced away from the pipe-shaped through electrode. A plurality of through electrodes are provided in substantially parallel within the inner region of the pipe-shaped through electrode.
摘要翻译：半导体器件设置有硅衬底和填充有通孔的结构，其具有矩形横截面并延伸穿过硅衬底。该结构包括管状贯通电极，条形穿通电极，硅，第一绝缘膜，第二绝缘膜和第三绝缘膜。管状贯通电极用作延伸穿过硅衬底的管状电导体。此外，条状贯通电极设置在管状贯通电极的内部，使得条状贯通电极延伸穿过硅衬底并与管状通电极间隔开。多个贯通电极大致平行地设置在管状贯通电极的内部区域内。

13. 发明授权

US07145247B2 Offset-bonded, multi-chip semiconductor device 失效
标题翻译：偏移式多芯片半导体器件
公开(公告)号：US07145247B2
公开(公告)日：2006-12-05
申请号：US10995491
申请日：2004-11-24
申请人： Masaya Kawano , Satoshi Matsui
发明人： Masaya Kawano , Satoshi Matsui
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06555 , H01L2225/06562 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： The present invention is aimed at bonding a lower chip and an upper chip through bumps in a highly reliable manner, while ensuring a sufficient area for an external connection terminal region, by offsetting the upper chip to the lower chip. The substrate 2 has bumps 1 arranged on one surface thereof, and has a first chip 3 mounted on the other surface thereof. A second chip 4 is bonded to the first chip 3 through bumps 5, 6 while offsetting the second chip 4 to the first chip 3 in parallel. In the bonded state of the first chip 3 and the second chip 4, a part of the first chip 3 and a part of the second chip 4 are overlapped without aligning the centers of the both. The center of gravity of the second chip 4 falls inside a region surrounded by the outermost bumps between the first chip 3 and the second chip 4.
摘要翻译：本发明的目的在于通过将上芯片与下芯片相抵消，以高可靠性的方式将下芯片和上芯片焊接在一起，同时确保足够的外部连接端子区域。基板2在其一个表面上具有凸块1，并且具有安装在其另一个表面上的第一芯片3。第二芯片4通过凸块5,6接合到第一芯片3，同时平行地将第二芯片4与第一芯片3抵消。在第一芯片3和第二芯片4的接合状态下，第一芯片3的一部分和第二芯片4的一部分重叠而不对准两者的中心。第二芯片4的重心落在由第一芯片3和第二芯片4之间的最外侧的凸块包围的区域内。

14. 发明申请

US20060006539A1 Semiconductor device and semiconductor module employing thereof 有权
标题翻译：半导体装置及其半导体模块
公开(公告)号：US20060006539A1
公开(公告)日：2006-01-12
申请号：US11167162
申请日：2005-06-28
申请人： Satoshi Matsui , Masaya Kawano
发明人： Satoshi Matsui , Masaya Kawano
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/585 , H01L24/05 , H01L2224/0401 , H01L2224/05009 , H01L2224/05551 , H01L2224/05552 , H01L2224/05553 , H01L2224/05555 , H01L2224/13025 , H01L2224/14181 , H01L2224/16 , H01L2224/16146 , H01L2224/16225 , H01L2225/06513
摘要： A semiconductor device 100 is provided with a silicon substrate 101 and a structure 120 filled in a through hole that has a rectangular cross section and extends through the silicon substrate 101. The structure 120 comprises a pipe-shaped through electrode 103, stripe-shaped through electrodes 107, silicons 105, a first insulating film 109, a second insulating film 111 and a third insulating film 113. The pipe-shaped through electrode 103 is utilized as a pipe-shaped electric conductor that extends through the silicon substrate 101. In addition, the stripe-shaped through electrodes 107 are provided in the interior of the pipe-shaped through electrode 103 so that the stripe-shaped through electrodes 107 extend through the silicon substrate 101 and is spaced away from the pipe-shaped through electrode 103. A plurality of through electrodes 107 are provided in substantially parallel within the inner region of the pipe-shaped through electrode 103.
摘要翻译：半导体器件100设置有硅衬底101和填充在具有矩形横截面并延伸穿过硅衬底101的通孔中的结构120。结构120包括管状通孔电极103，条形通孔电极107，硅酮105，第一绝缘膜109，第二绝缘膜111和第三绝缘膜113。管状贯通电极103用作延伸穿过硅衬底101的管状电导体。此外，条状贯通电极107设置在管状贯通电极103的内部，使得条形通孔电极107延伸穿过硅衬底101并与管状通电极103间隔开。多个贯通电极107大致平行地设置在管状贯通电极103的内部区域内。

15. 发明授权

US08511272B2 Accessory mounting structure 有权
标题翻译：附件安装结构
公开(公告)号：US08511272B2
公开(公告)日：2013-08-20
申请号：US12268257
申请日：2008-11-10
申请人： Kazuaki Koyama , Sumito Hori , Satoshi Matsui
发明人： Kazuaki Koyama , Sumito Hori , Satoshi Matsui
IPC分类号： F02B67/00
CPC分类号： F02B67/00 , F02F7/0068
摘要： A horizontal groove extending horizontally when an alternator bracket is fixed to a cylinder block of a vehicle engine is formed in the alternator bracket. A shank of a bolt inserted through mounting pieces of an alternator is inserted into the horizontal groove from a horizontally lateral direction toward the cylinder block to support the bolt on a lower surface of the horizontal groove. After insertion, the bolt is restrained from moving toward an opening of the horizontal groove. Since the insertion of the bolt into the horizontal groove is facilitated, and the weight of the alternator is borne by the lower surface of the horizontal groove, a burden on a fixing portion is reduced, and it becomes easy to position the alternator and hold it when it is fixed. Thus, the accessory can be mounted on the cylinder block with satisfactory work efficiency and with support accuracy kept high.
摘要翻译：在交流发电机支架上形成有将交流发电机支架固定在车辆发动机的气缸体上时水平延伸的水平槽。通过交流发电机的安装件插入的螺栓的柄部从水平方向朝向气缸体插入到水平槽中，以将螺栓支撑在水平槽的下表面上。插入后，螺栓被限制向水平槽的开口移动。由于容易将螺栓插入水平槽中，并且交流发电机的重量由水平槽的下表面承担，所以固定部分的负担减小，容易定位交流发电机并保持当它是固定的。因此，附件可以以令人满意的工作效率安装在气缸体上，并且支撑精度保持较高。

16. 发明申请

US20080222436A1 POWER SUPPLY VOLTAGE REGULATOR CIRCUIT AND MICROCOMPUTER 有权
标题翻译：电源电压调节器电路和微型计算机
公开(公告)号：US20080222436A1
公开(公告)日：2008-09-11
申请号：US12043506
申请日：2008-03-06
申请人： Satoshi Matsui
发明人： Satoshi Matsui
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/32
摘要： A power supply voltage regulator circuit including a power supply circuit which switches to a first through a fourth state; the first state being the state wherein voltage is supplied to neither a normal circuit nor a backup system circuit based on the combination of logic for the normal circuit power control signal, the second state being the state wherein a primary power supply voltage is supplied to the normal circuit and a secondary power supply voltage is supplied to the backup system circuit, the third state being the state wherein voltage is not supplied to the normal circuit and the secondary power supply voltage is supplied to the backup system circuit, the fourth state being the state wherein the primary power supply voltage is supplied to both the normal circuit and the backup system circuit.
摘要翻译：一种电源稳压器电路，包括切换到第一至第四状态的电源电路; 第一状态是基于用于正常电路功率控制信号的逻辑的组合而不向正常电路和备用系统电路供应电压的状态，第二状态是向第一状态提供主电源电压的状态正常电路和次级电源电压被提供给备用系统电路，第三状态是其中电压不被提供给正常电路并且次级电源电压被提供给备用系统电路的状态，第四状态是其中主电源电压被提供给正常电路和备用系统电路。

17. 发明申请

US20070004084A1 Chip and multi-chip semiconductor device using thereof and method for manufacturing same 有权
标题翻译：使用其的芯片和多芯片半导体器件及其制造方法
公开(公告)号：US20070004084A1
公开(公告)日：2007-01-04
申请号：US11518274
申请日：2006-09-11
申请人： Satoshi Matsui
发明人： Satoshi Matsui
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L25/50 , H01L23/481 , H01L23/49827 , H01L23/49833 , H01L23/544 , H01L24/81 , H01L25/0657 , H01L2223/54473 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/81136 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , Y10S438/975 , H01L2924/00 , H01L2924/00014
摘要： The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process step to the formation process for the marking for alignment. In the chip for the multi-chip semiconductor device having two or more electroconductive through plug in one chip for the multi-chip semiconductor device, one or more electroconductive through plugs are employed for the marking for alignment, and the chip is configured to allow identification of the marking for alignment on the front surface and/or the back surface of the chip for the multi-chip semiconductor device. Then, an insulating film is provided on the front surface and/or the back surface of the electrically conducting through plug.
摘要翻译：仅通过从芯片的前表面（光刻，蚀刻）的处理及其制造方法的仅在芯片的前表面和/或后表面上形成的用于对准的标记的多芯片半导体器件的芯片而不需要为对准标记的形成过程添加任何专门的工艺步骤。在具有用于多芯片半导体器件的一个芯片中具有两个或多个导电贯穿插头的多芯片半导体器件的芯片中，采用一个或多个导电通孔用于对准的标记，并且芯片被配置为允许识别用于在用于多芯片半导体器件的芯片的前表面和/或背表面上对准的标记。然后，在导电贯通插头的前表面和/或后表面上设置绝缘膜。

18. 发明申请

US20060118965A1 Semiconductor device, semiconductor module employing thereof and method for manufacturing semiconductor device 有权
标题翻译：半导体器件，其半导体模块及半导体器件的制造方法
公开(公告)号：US20060118965A1
公开(公告)日：2006-06-08
申请号：US11290433
申请日：2005-12-01
申请人： Satoshi Matsui
发明人： Satoshi Matsui
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L25/0657 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A plurality of columnar through plugs 107 are provided in the insulating film 105.
摘要翻译：衬底的水平面中的贯通电极的配置密度提高。提供延伸穿过硅衬底101的通孔103。绝缘膜105被埋在通孔103内。绝缘膜105中设有多个柱状贯通插头107。

19. 发明申请

US20050252463A1 Cylinder head structure 有权
标题翻译：气缸盖结构
公开(公告)号：US20050252463A1
公开(公告)日：2005-11-17
申请号：US11125143
申请日：2005-05-10
申请人： Satoshi Matsui , Toshihiko Oka , Koichi Yoshimoto , Yoshinori Sakurai , Tetsushi Nagira , Kenichi Morishima
发明人： Satoshi Matsui , Toshihiko Oka , Koichi Yoshimoto , Yoshinori Sakurai , Tetsushi Nagira , Kenichi Morishima
IPC分类号： F02F1/38 , F01P3/02 , F02B31/00 , F02F1/24 , F02F1/26 , F02F1/36 , F02F1/40 , F02F1/42
CPC分类号： F02F1/40 , F02B31/00
摘要： The bottom surface 18 of the cylinder head 10 is formed by an intake-side bottom surface 18a and an exhaust-side bottom surface 18b on which an intake port 13 and an exhaust port 15 are formed respectively. Further, a first wall 19 formed between an intake-side water jacket 16 and the intake-side bottom surface 18a is larger in thickness than a second wall 20 formed between an exhaust-side water jacket 17 and the exhaust-side bottom surface 18b. This structure can reduce an amount of HC included in exhaust gas.
摘要翻译：气缸盖10的底表面18由分别形成有进气口13和排气口15的进气侧底面18a和排气侧底面18b形成。此外，形成在进气侧水套16和进气侧底面18a之间的第一壁19的厚度大于形成在排气侧水套17和排气侧底面18之间的第二壁20 b。该结构可以减少废气中包含的HC的量。

20. 发明申请

US20050182885A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050182885A1
公开(公告)日：2005-08-18
申请号：US10898339
申请日：2004-07-26
申请人： Satoshi Matsui , Seiji Suetake
发明人： Satoshi Matsui , Seiji Suetake
IPC分类号： G06F12/04 , G06F13/16 , G06F13/40
CPC分类号： G06F13/1678 , G06F13/4018
摘要： A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal address signal outputted from a controller and outputs the selected bits as an external address signal. Specifically, the address controlling unit selects upper bits of the internal address signal when the bus width of the external data signal is increased according to the mode signal. Therefore, it is possible to prevent occurrence of an unused external address terminal, enabling the increase in accessible external memory capacity.
摘要翻译：数据控制单元根据模式信号激活预定数量的数据终端并改变外部数据信号的总线宽度。根据模式信号，地址控制单元选择从控制器输出的内部地址信号的预定数量的比特，并将所选择的比特输出为外部地址信号。具体地说，当根据模式信号增加外部数据信号的总线宽度时，地址控制单元选择内部地址信号的高位。因此，可以防止未使用的外部地址端子的发生，从而能够增加可访问的外部存储器容量。

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