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11. 发明申请

US20090024128A1 EXTERNAL SKELETAL FIXATION DEVICE 有权
标题翻译：外固定装置
公开(公告)号：US20090024128A1
公开(公告)日：2009-01-22
申请号：US11885484
申请日：2005-03-03
申请人： Kozo Nakamura , Isao Ohnishi , Masahiko Bessho , Satoru Oohashi , Tsuneo Aoki , Mitsuo Sato , Ryojiro Asano , Kazuo Watanabe , Hiroshi Matsuzawa , Toshiro Uehara , Yoshiharu Saito
发明人： Kozo Nakamura , Isao Ohnishi , Masahiko Bessho , Satoru Oohashi , Tsuneo Aoki , Mitsuo Sato , Ryojiro Asano , Kazuo Watanabe , Hiroshi Matsuzawa , Toshiro Uehara , Yoshiharu Saito
IPC分类号： A61B17/00
CPC分类号： A61B17/6483 , A61B17/6416 , A61B17/6425 , A61B17/6466
摘要： An external skeletal fixation device reduces load on the patient, is capable of freely moving and deformity correction of a bone and bone fragments, is simple in construction and can be attached to the patient by an operator who has not a very high skill and long experience. An external skeletal fixation device 1 includes a pair of pin clamp units 2 and 3 fixedly holding rodlike members 61 and 62 inserted, respectively, into a first part 9B2 and a second part 9B3 of a bone 9B on the opposite sides, respectively, of a virtual hinge point 9B1 in the bone 9B. The virtual hinge point corresponds to a center of rotational angulation of the bone, a center on which the first and the second part of the bone respectively on the opposite sides of a fracture site of the bone or a part of the osteotomy site for deformity correction are turned, or a center about which a joint turns. A connecting mechanism 4 connecting the pair of pin clamp units 2 and 3 has a pair of arms 41 and 42 pivotally connected to the pair of pin clamp units 2 and 3, respectively. The pair of arms 41 and 42 are pivotally joined together. The respective axes A1, B1 and C1 of rotary joints A, B and C respectively connecting the pin clamp units 2 and the arm 41, the pin clamp unit 3 and the arm 42, and the arms 41 and 42 extend toward the virtual hinge point 9B1.
摘要翻译：外部骨骼固定装置减轻患者的负担，能够自由移动和骨骼和骨碎片的畸形矫正，结构简单，并且可以由技能不高和经验丰富的操作者附着在患者身上。外部骨骼固定装置1包括固定地保持杆状构件61和62的一对销夹紧单元2和3，其分别插入到相对侧的骨9B的第一部分9B2和第二部分9B3中骨9B中的虚拟铰接点9B1。虚拟铰链点对应于骨的旋转角度的中心，骨骼的第一部分和第二部分分别在骨骼的骨折部位的相对侧上的中心或用于畸形矫正的截骨部位的一部分被转动，或关节绕其转动的中心。连接一对针夹单元2和3的连接机构4分别具有一对臂41和42，该一对臂41和42分别枢转地连接到一对针夹单元2和3。一对臂41和42枢转地连接在一起。分别连接销夹单元2和臂41，销夹单元3和臂42以及臂41和42的旋转接头A，B和C的各轴线A1，B1和C1朝向虚拟铰链点 9B1。

12. 发明授权

US07405005B2 Display apparatus and antireflection substance 失效
标题翻译：显示装置和防反射物质
公开(公告)号：US07405005B2
公开(公告)日：2008-07-29
申请号：US10250579
申请日：2002-11-06
申请人： Kazuo Watanabe
发明人： Kazuo Watanabe
IPC分类号： B32B17/00
CPC分类号： G02B1/11 , G02B1/115
摘要： The present invention provides an antireflection substance such as an antireflection film having a low moisture-permeable characteristic, high quality and high reliability, and also provides a display apparatus comprising this antireflection substance. The antireflection substance according to the present invention includes an antireflection film formed on a transparent substrate, the antireflection film being composed of a multiple layer in which a first layer serving as an adhesion-improving layer, a second layer serving as a barrier layer against moisture, a third layer, a fourth layer and a fifth layer are laminated in this order, and in which the second layer and the fourth layer are each set to have a refractive index higher than that of the third layer and the fifth layer. The display apparatus according to the present invention comprises this antireflection substance on its display surface.
摘要翻译：本发明提供了具有低透湿特性，高品质和高可靠性的抗反射膜等抗反射物质，并且还提供了一种包含该防反射物质的显示装置。根据本发明的抗反射物质包括形成在透明基板上的抗反射膜，该防反射膜由多层构成，其中第一层用作粘合改进层，第二层用作阻挡层，第三层，第四层和第五层依次层叠，并且其中第二层和第四层的折射率分别高于第三层和第五层的折射率。根据本发明的显示装置在其显示表面上包括该抗反射物质。

13. 发明申请

US20070142080A1 Direct-conversion transmitter circuit and transceiver system 有权
公开(公告)号：US20070142080A1
公开(公告)日：2007-06-21
申请号：US11703166
申请日：2007-02-07
申请人： Satoshi Tanaka , Taizo Yamawaki , Kazuaki Hori , Kazuo Watanabe
发明人： Satoshi Tanaka , Taizo Yamawaki , Kazuaki Hori , Kazuo Watanabe
IPC分类号： H04B1/44 , H04M1/00
CPC分类号： H03D3/007 , H03C3/40 , H04B1/30
摘要： Disclosed is a direct conversion type transmitter or transceiver circuit suitable for a mobile communication device which corresponds to broad signal output level variable width to be required by W-CDMA, which does not necessitate any high-performance low noise VCO and RF filter, capable of reducing a number of components and the cost. In the input portion of an orthogonal modulator composed of a divider, mixers, and a common load, there are provided variable attenuators. If an input signal level of the orthogonal modulator within the transmitter circuit lowers, this variable attenuator circuit is operated so as to lower the bias of the orthogonal modulator to reduce the amount of occurrence of carrier leak, and to prevent the signal during low output level and carrier leak ratio from being deteriorated. The direct conversion transmitter circuit is capable of easily realizing output level variable width of 70 dB or higher and reducing a variable amount in the high frequency circuit in which it is difficult to secure the variable gain width.

14. 发明申请

US20060049878A1 Phase locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US20060049878A1
公开(公告)日：2006-03-09
申请号：US11202266
申请日：2005-08-12
申请人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03C3/0925 , H03C3/0941 , H03C3/0991 , H03L7/1974 , H03L7/1976
摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
摘要翻译：本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

15. 发明申请

US20050186927A1 Signal processing semiconductor integrated circuit device and wireless communication system 有权
标题翻译：信号处理半导体集成电路器件和无线通信系统
公开(公告)号：US20050186927A1
公开(公告)日：2005-08-25
申请号：US11111934
申请日：2005-04-22
申请人： Norio Hayashi , Noriyoshi Hagino , Toshiki Matsui , Kazuo Watanabe , Satoshi Tanaka
发明人： Norio Hayashi , Noriyoshi Hagino , Toshiki Matsui , Kazuo Watanabe , Satoshi Tanaka
IPC分类号： H03D7/14 , H04B1/30 , H04B1/3822 , H04B1/40 , H04B1/06 , H04B7/00
CPC分类号： H04B1/30 , H03D7/1433 , H03D7/1458 , H03D2200/0033 , H03D2200/0047 , H03D2200/009
摘要： The invention provides a signal processing semiconductor integrated circuit of the direct conversion system, which includes a dummy amplifier having the same circuit configuration as a low noise amplifier being the first stage amplifier, in which the DC offset calibrations on the subsequent stage amplifiers are carried out during shifting into the reception mode in a state that the low noise amplifier is deactivated and the dummy amplifier is activated. Thereby, the invention achieves to suppress generation of the DC offsets resulting from the leakage noises of the local oscillator during shifting into the reception mode, and to enhance the reception sensitivity.
摘要翻译：本发明提供一种直接转换系统的信号处理半导体集成电路，其包括具有与作为第一级放大器的低噪声放大器相同的电路结构的虚拟放大器，其中在后级放大器上进行DC偏移校准在低噪声放大器被去激活并且虚拟放大器被激活的状态下转换到接收模式期间。由此，本发明实现了抑制在变换为接收模式时本地振荡器的泄漏噪声产生的DC偏移的产生，并提高了接收灵敏度。

16. 发明授权

US06912380B2 PLL circuit and wireless mobile station with that PLL circuit 失效
标题翻译： PLL电路和具有该PLL电路的无线移动台
公开(公告)号：US06912380B2
公开(公告)日：2005-06-28
申请号：US09819810
申请日：2001-03-29
申请人： Taizo Yamawaki , Satoshi Tanaka , Norio Hayashi , Kazuo Watanabe , Robert Astle Henshaw
发明人： Taizo Yamawaki , Satoshi Tanaka , Norio Hayashi , Kazuo Watanabe , Robert Astle Henshaw
IPC分类号： H03L7/093 , H03L7/07 , H03L7/08 , H03L7/085 , H03L7/10 , H04B1/40 , H04L27/152 , H04B1/06
CPC分类号： H03L7/085 , H03L7/07 , H03L7/10 , H03L2207/12
摘要： In a PLL circuit, and a wireless mobile station with that PLL circuit, an LPF charging constant current source, a discharging constant current source and a high-speed charging constant current source are connected to an output terminal of a phase comparator with current mode output. When a convergence frequency of the PLL circuit is low, an input voltage of a VCO is increased from OV so as to be converged by using the constant current source. However, when the convergence frequency of the PLL circuit is high, the input voltage of the PLL circuit is temporarily increased to the maximum voltage by using the constant current source. Thereafter, the input voltage is gradually dropped from the maximum voltage so as to be converged by using the constant current source.
摘要翻译：在PLL电路和具有该PLL电路的无线移动站中，LPF充电恒流源，放电恒流源和高速充电恒流源连接到具有电流模式输出的相位比较器的输出端。当PLL电路的收敛频率低时，VCO的输入电压从0V增加，以便通过使用恒流源而被收敛。然而，当PLL电路的收敛频率高时，通过使用恒流源将PLL电路的输入电压临时增加到最大电压。此后，输入电压从最大电压逐渐降低，以便通过使用恒流源来收敛。

17. 发明授权

US06909882B2 Signal processing semiconductor integrated circuit device and wireless communication system 有权
公开(公告)号：US06909882B2
公开(公告)日：2005-06-21
申请号：US10033793
申请日：2002-01-03
申请人： Norio Hayashi , Noriyoshi Hagino , Toshiki Matsui , Kazuo Watanabe , Satoshi Tanaka
发明人： Norio Hayashi , Noriyoshi Hagino , Toshiki Matsui , Kazuo Watanabe , Satoshi Tanaka
IPC分类号： H03D7/14 , H04B1/30 , H04B1/3822 , H04B1/40
CPC分类号： H04B1/30 , H03D7/1433 , H03D7/1458 , H03D2200/0033 , H03D2200/0047 , H03D2200/009
摘要： The invention provides a signal processing semiconductor integrated circuit of the direct conversion system, which includes a dummy amplifier having the same circuit configuration as a low noise amplifier being the first stage amplifier, in which the DC offset calibrations on the subsequent stage amplifiers are carried out during shifting into the reception mode in a state that the low noise amplifier is deactivated and the dummy amplifier is activated. Thereby, the invention achieves to suppress generation of the DC offsets resulting from the leakage noises of the local oscillator during shifting into the reception mode, and to enhance the reception sensitivity.

18. 发明授权

US06826388B1 Mobile communication apparatus including dividers in transmitter and receiver 有权
标题翻译：移动通信设备包括发射机和接收机中的分频器
公开(公告)号：US06826388B1
公开(公告)日：2004-11-30
申请号：US09711105
申请日：2000-11-14
申请人： Satoshi Tanaka , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
发明人： Satoshi Tanaka , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
IPC分类号： H04B140
CPC分类号： H04B1/30 , H03D2200/0047 , H03K21/16
摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
摘要翻译：适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除消除。

19. 发明授权

US06646582B2 Error compensation for sigma-delta modulated digital signals or the like 失效
标题翻译： Σ-Δ调制数字信号的误差补偿等
公开(公告)号：US06646582B2
公开(公告)日：2003-11-11
申请号：US10215624
申请日：2002-08-09
申请人： Kazuo Watanabe
发明人： Kazuo Watanabe
IPC分类号： H03M300
CPC分类号： H03M7/3006
摘要： A noise control system for use in an SACD player in order to compensate for errors in the recovered delta-sigma modulated audio signal in which each sample of the original analog signal is expressed by either binary 0 or 1. Included is an error-detecting and -correcting circuit for detecting and, if possible, correcting errors in the primary data of the digital signal. An interpolation data generator is provided which repeatedly puts out a predefined interpolation datum for insertion in each uncorrectable or uncorrected error location in the digital signal whenever such an error is detected by the error-detecting and -correcting circuit. The interpolation datum is constituted of equal numbers of binary 0s and 1s, which are so arranged as to represent a frequency in excess of the audible range of frequencies.
摘要翻译：一种用于SACD播放器的噪声控制系统，用于补偿恢复的delta-sigma调制音频信号中的错误，其中原始模拟信号的每个样本由二进制0或1表示。包括错误检测和校正电路，用于检测并且如果可能的话，校正数字信号的主数据中的错误。提供一种内插数据发生器，每当由误差检测和校正电路检测到这种误差时，该数字信号反复地输出用于在每个不可校正或未校正的错误位置插入的预定内插数据。内插数据由相等数量的二进制0和1组成，它们被布置为表示超过可听频率范围的频率。

20. 发明授权

US06639933B2 Phase-locked loop circuit and radio communication apparatus using the same 有权
公开(公告)号：US06639933B2
公开(公告)日：2003-10-28
申请号：US09993764
申请日：2001-11-27
申请人： Taizo Yamawaki , Masaru Kokubo , Tomio Furuya , Kazuo Watanabe , Julian Hildersley
发明人： Taizo Yamawaki , Masaru Kokubo , Tomio Furuya , Kazuo Watanabe , Julian Hildersley
IPC分类号： H03D324
CPC分类号： H03L7/085 , H03L7/10 , H03L7/183 , H03L2207/12 , H04B1/403 , H04B1/408
摘要： A communication apparatus includes a phase-locked loop circuit which receives a first signal having a frequency and converts it into an output signal having a transmission frequency, and includes a current output type phase comparator which converts a phase difference between the first signal and a second signal into a current signal, a low pass filter which filters the current signal of the current output type phase comparator to produce an output signal, a voltage controlled oscillator which produces an output signal having a transmission frequency corresponding to the output signal of the low pass filter, the output signal of the voltage controlled oscillator constituting the output signal of the phase-locked loop circuit, a frequency converter which frequency-converts the output signal of the voltage controlled oscillator to produce the second signal, and a current source which supplies a current to an input of the low pass filter.

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