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11. 发明授权

US4503600A Process for manufacturing a buried gate field effect transistor 失效
标题翻译：掩埋栅场效应晶体管的制造工艺
公开(公告)号：US4503600A
公开(公告)日：1985-03-12
申请号：US466578
申请日：1983-02-15
申请人： Riro Nii , Nobuyuki Toyoda , Akimichi Hojo
发明人： Riro Nii , Nobuyuki Toyoda , Akimichi Hojo
IPC分类号： H01L21/285 , H01L21/335 , H01L21/338 , H01L29/417 , H01L29/423 , H01L29/778 , H01L29/80 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/42316 , H01L29/7787 , H01L29/80
摘要： A process for manufacturing a buried gate field effect transistor having a small effective gate length, which process enables precise control of the threshold voltage. First, a compound semiconductor crystal having a first impurity region as a source region, a second impurity region as a drain region and a channel layer buried inside the compound semiconductor crystal is prepared by a conventional process. A V-shaped groove is then formed with an etching solution having high selectivity toward the crystal face in the gate region of this compound semiconductor crystal. Onto the inner wall surface of the V-shaped groove, a metal likely to form an alloy type of Schottky junction with the compound semiconductor is vapor-deposited. The resultant structure is heated, while measuring the threshold voltage, to form an alloy type of Schottky junction and for use of this junction as a gate electrode.
摘要翻译：一种具有小的有效栅极长度的掩埋栅极场效应晶体管的制造方法，能够精确地控制阈值电压。首先，通过常规方法制备具有作为源极区的第一杂质区域，作为漏极区域的第二杂质区域和埋在化合物半导体晶体内的沟道层的化合物半导体晶体。然后用对化合物半导体晶体的栅极区域中的晶面具有高选择性的蚀刻溶液形成V形槽。在V形槽的内壁表面上，气化沉积可能与化合物半导体形成合金型肖特基结的金属。所得结构在测量阈值电压的同时被加热以形成合金型肖特基结，并用于该结作为栅电极。

12. 发明授权

US08354468B2 Thermoplastic elastomer composition 有权
标题翻译：热塑性弹性体组合物
公开(公告)号：US08354468B2
公开(公告)日：2013-01-15
申请号：US12921315
申请日：2009-03-05
申请人： Nobuyuki Toyoda , Kentarou Kanae , Hideo Nakanishi , Masato Kobayashi
发明人： Nobuyuki Toyoda , Kentarou Kanae , Hideo Nakanishi , Masato Kobayashi
IPC分类号： C08J3/22 , C08L23/00
CPC分类号： C08L23/08 , C08K5/01 , C08K5/14 , C08L23/0815 , C08L2205/02 , C08L2666/06
摘要： A thermoplastic elastomer composition that exhibits excellent rubber elasticity, etc. is obtained by dynamically heating a polymer composition in the presence of the crosslinking agent, the polymer composition including an α-olefin thermoplastic resin (A), and an oil-extended ethylene copolymer (B) that includes an ethylene copolymer that satisfies given conditions, and 50 to 150 parts by mass of a first mineral oil-based softener based on 100 parts by mass of the ethylene copolymer, the content of the oil-extended ethylene copolymer (B) being 30 mass % or more based on the total amount (=100 mass %) of the polymer component including the α-olefin thermoplastic resin (A) and the oil-extended ethylene copolymer (B).
摘要翻译：通过在交联剂的存在下动态加热聚合物组合物，包含α-烯烃热塑性树脂（A）和油延伸乙烯共聚物（A）的聚合物组合物，获得具有优异的橡胶弹性等的热塑性弹性体组合物 B），其包含满足规定条件的乙烯共聚物和基于100质量份乙烯共聚物的50〜150质量份的第一矿物油系软化剂，含油乙烯共聚物（B）的含量，基于包括α-烯烃热塑性树脂（A）和油延伸乙烯共聚物（B）的聚合物组分的总量（= 100质量％）为30质量％以上。

13. 发明申请

US20060131934A1 Vehicle roof structure 有权
标题翻译：车顶结构
公开(公告)号：US20060131934A1
公开(公告)日：2006-06-22
申请号：US11300921
申请日：2005-12-15
申请人： Tadayuki Uchida , Harutaka Maruyama , Nobuyuki Toyoda , Etsuko Karube
发明人： Tadayuki Uchida , Harutaka Maruyama , Nobuyuki Toyoda , Etsuko Karube
IPC分类号： B62D25/06
CPC分类号： B60R9/058
摘要： In a vehicle roof structure, a roof panel has a central opening in which a roof glass is supported. A roof molding is mounted to molding mounting grooves that are formed along connecting portions between the roof panel and roof side rails extending along the roof panel. The roof molding includes a molding body and support legs. The molding body also includes: a lip portion that is formed at one side edge thereof and protrudes out of the molding mounting groove to cover a peripheral edge of the roof glass; and an inclined portion which is formed at the other side edge thereof and is inclined smoothly toward a bottom of the molding mounting groove. Therefore, the molding body continuously covers a region from the roof glass to the roof side rail, thereby improving the appearance, and further makes inconspicuous a recess defined by the molding mounting groove and the inclined portion, thereby minimizing the influence of the recess on the roof appearance, while rain water coming from the side of the roof panel is prevented from flowing over the roof side rail.
摘要翻译：在车顶结构中，屋顶板具有支撑屋顶玻璃的中心开口。安装屋顶模制件以模制安装槽，所述安装槽沿着顶板延伸的顶板和屋顶侧轨之间的连接部分形成。屋顶成型件包括成型体和支撑腿。成形体还包括：唇部，其形成在其一个侧边缘处并从成型安装槽突出以覆盖屋顶玻璃的周边边缘; 以及形成在其另一侧边缘的倾斜部分，并且朝着成型安装槽的底部平滑地倾斜。因此，成型体连续地覆盖从屋顶玻璃到屋顶侧轨道的区域，从而改善外观，并且进一步使由模制安装槽和倾斜部限定的凹部不显眼，从而最小化凹部对屋顶外观，同时防止从屋顶板侧面流出的雨水流过屋顶侧轨。

14. 发明授权

US5015596A Method of making a GaAs JFET with self-aligned p-type gate by outdiffusion of dopont from the metallic gate 失效
标题翻译：通过从金属栅极扩散dopont制造具有自对准p型栅极的GaAs JFET的方法
公开(公告)号：US5015596A
公开(公告)日：1991-05-14
申请号：US476140
申请日：1990-02-08
申请人： Nobuyuki Toyoda , Naotaka Uchitomi , Akimichi Hojo
发明人： Nobuyuki Toyoda , Naotaka Uchitomi , Akimichi Hojo
IPC分类号： H01L21/337 , H01L29/417 , H01L29/45 , H01L29/808
CPC分类号： H01L29/808 , H01L29/452 , Y10S148/082 , Y10S148/088
摘要： A GaAs JFET according to the present invention is formed as follows. First, an n type active layer is formed on a GaAs substrate. Then, a gate electrode containing a group II element is formed on the n type active layer. With the gate electrode being used as a mask, an n type impurity is ion-implanted in the GaAs substrate with a high concentration in a self-aligned fashion with respect to the gate electrode. Heat-treatment is then performed on the resultant structure to diffuse the group II element in the gate electrode into the n type active layer, forming a p type gate region. At the same time, the ion-implanted n type impurity is activated, forming source and drain regions.
摘要翻译：根据本发明的GaAs JFET如下形成。首先，在GaAs衬底上形成n型有源层。然后，在n型有源层上形成含有II族元素的栅电极。以栅电极作为掩模，n型杂质以相对于栅电极的自对准方式以高浓度离子注入到GaAs衬底中。然后在所得结构上进行热处理，将栅电极中的II族元素扩散到n型有源层中，形成p型栅区。同时，离子注入的n型杂质被激活，形成源区和漏区。

15. 发明授权

US4663646A Gate array integrated circuit using Schottky-barrier FETs 失效
标题翻译：使用肖特基势垒FET的门阵列集成电路
公开(公告)号：US4663646A
公开(公告)日：1987-05-05
申请号：US674869
申请日：1984-11-26
申请人： Yasuo Ikawa , Nobuyuki Toyoda , Katsue Kanazawa , Takamaro Mizoguchi , Akimichi Hojo
发明人： Yasuo Ikawa , Nobuyuki Toyoda , Katsue Kanazawa , Takamaro Mizoguchi , Akimichi Hojo
IPC分类号： H01L27/095 , G11C5/02 , G11C5/06 , G11C5/14 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118
CPC分类号： G11C5/063 , G11C5/02 , G11C5/14
摘要： A gate array integrated circuit in which gate cells are each composed of a DCFL circuit using Schottky-barrier FETs. A plurality of basic gate cells is arrayed in one direction to form a basic cell array, and such basic cell arrays are arranged parallel to each other. VDD lines and GND lines are provided to apply an operating voltage to the basic gate cells. In order to stably operate the gate array integrated circuit of DCFL structure in which the logical amplitude and noise margin are small, the VDD lines and the GND lines are arranged perpendicular to each other such that the number of the basic gate cells which are connected to each of the VDD lines is larger than that of the basic gate cells which are connected to each of the GND lines. According to this layout, the potential difference (voltage drop) developed in the GND lines by operation current is reduced.
摘要翻译：门阵列集成电路，其中栅极单元由使用肖特基势垒FET的DCFL电路组成。多个基本栅极单元沿一个方向排列以形成基本单元阵列，并且这些基本单元阵列彼此平行布置。提供VDD线和GND线以向基本门单元施加工作电压。为了稳定地操作逻辑幅度和噪声容限小的DCFL结构的门阵列集成电路，VDD线和GND线彼此垂直布置，使得连接到每条VDD线都大于连接到每条GND线的基本栅极单元。根据该布局，通过工作电流在GND线上产生的电位差（电压降）降低。

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