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11. 发明申请

US20100060332A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20100060332A1
公开(公告)日：2010-03-11
申请号：US12340912
申请日：2008-12-22
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/06
CPC分类号： H03K3/0322 , H03K5/1504 , H03K2005/00208 , H03L7/083 , H03L7/24
摘要： A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.
摘要翻译：半导体集成电路包括PLL（锁相环）电路，其被配置为响应于参考时钟信号的频率产生控制电压，并且产生具有对应于控制电平的频率的PLL时钟信号电压和被配置为响应于PLL时钟信号而振荡输出时钟信号的压控振荡器，并且允许PLL时钟信号具有对应于控制电压电平的频率。

12. 发明申请

US20090206901A1 DUTY CYCLE CORRECTION CIRCUIT WITH REDUCED CURRENT CONSUMPTION 失效
标题翻译：具有降低电流消耗的占空比校正电路
公开(公告)号：US20090206901A1
公开(公告)日：2009-08-20
申请号：US12333193
申请日：2008-12-11
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Jae Min Jang , Hyung Soo Kim , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
IPC分类号： H03K5/04
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.
摘要翻译：一种占空比校正电路包括：信号产生单元，包括耦合到电源电压端并被配置为响应于时钟信号输出输出信号的互补输出信号的第一信号产生单元，以及耦合到所述电源电压端子被配置为响应于所述时钟信号的互补时钟信号而输出所述输出信号; 耦合在第一和第二信号发生单元之间的可变电阻器单元，被配置为根据占空比校正控制信号改变流入信号生成单元的电流量，该占空比校正控制信号具有基于电压电平输出信号; 以及耦合在可变电阻器单元和被配置为向信号产生单元提供电流的接地电压端子之间的电流源。

13. 发明授权

US08018265B1 Differential signal generation circuit 有权
标题翻译：差分信号发生电路
公开(公告)号：US08018265B1
公开(公告)日：2011-09-13
申请号：US12840255
申请日：2010-07-20
申请人： Yong Ju Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
发明人： Yong Ju Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC分类号： H03K5/13
CPC分类号： H03K5/1515
摘要： A differential signal generation circuit includes: an inverter array configured to sequentially invert an input signal to generate a plurality of delayed signals; and a phase mixer configured to mix a phase of a first delayed signal and a phase of a second delayed signal among the plurality of delayed signals at a preset mixing ratio to generate a first differential signal. The first delayed signal has a first delay from the input signal and the second delayed signal has a second delay from the input signal. The differential signal generation circuit is configured to generate a third delayed signal having a third delay from the input signal corresponding to a medium of the first and second delays, and the third delayed signal is further delayed to generate a second differential signal.
摘要翻译：差分信号发生电路包括：逆变器阵列，被配置为顺序地反转输入信号以产生多个延迟信号; 以及相位混合器，被配置为以预设的混合比混合多个延迟信号中的第一延迟信号的相位和第二延迟信号的相位，以产生第一差分信号。第一延迟信号具有来自输入信号的第一延迟，并且第二延迟信号具有来自输入信号的第二延迟。差分信号生成电路被配置为从与第一和第二延迟的介质相对应的输入信号产生具有第三延迟的第三延迟信号，并且第三延迟信号被进一步延迟以产生第二差分信号。

14. 发明申请

US20100309732A1 DATA ALIGNMENT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器的数据对准电路
公开(公告)号：US20100309732A1
公开(公告)日：2010-12-09
申请号：US12647174
申请日：2009-12-24
申请人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1078 , G11C7/1087
摘要： A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.
摘要翻译：用于接收和对准并行数据组的半导体存储装置的数据对准电路包括第一控制单元，第二控制单元，第一对准单元和第二对准单元。第一对准单元响应于地址组，时钟信号和等待时间信号产生第一控制信号组。第二控制单元响应于地址组，时钟信号和等待时间信号产生第二控制信号组。第一对准单元响应于第一控制信号组将并行数据组对准为第一串行数据组。第二对准单元响应于第二控制信号组将并行数据组对准为第二串行数据组。

15. 发明授权

US07800416B2 Data output buffer circuit 有权
标题翻译：数据输出缓冲电路
公开(公告)号：US07800416B2
公开(公告)日：2010-09-21
申请号：US12340882
申请日：2008-12-22
申请人： Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03K3/00
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C11/4093
摘要： A data output circuit includes a pre-driving block configured to receive input data, generate a plurality of pull-up signals and pull-down signals, and change enable times of the pull-up signals and the pull-down signals in response to a plurality of control signals, and a main driving block configured to generate output data in response to the pull-up signals and the pull-down signals.
摘要翻译：数据输出电路包括：预驱动块，被配置为接收输入数据，产生多个上拉信号和下拉信号，以及响应于一个上拉信号和下拉信号改变使能时间多个控制信号和主驱动块，被配置为响应于上拉信号和下拉信号而产生输出数据。

16. 发明申请

US20100064163A1 DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器装置的域交叉电路
公开(公告)号：US20100064163A1
公开(公告)日：2010-03-11
申请号：US12346675
申请日：2008-12-30
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G06F1/12
CPC分类号： G11C7/1051 , G06F1/12 , G11C7/1072 , G11C7/222
摘要： A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.
摘要翻译：半导体存储器装置的域交叉电路，域交叉电路包括在基本上相同的时钟周期产生的第一和第二计数信号，并且相对于相同位组合数据参考内部时钟信号表示预定的时钟差，以及数据处理单元，被配置为响应于与外部时钟信号同步的输入数据，基于第二计数信号提供对应于输入数据的输出数据。

17. 发明申请

US20100034043A1 SEMICONDUCTOR IC DEVICE HAVING POWER-SHARING AND METHOD OF POWER-SHARING THEREOF 失效
标题翻译：具有动力共享的半导体IC器件及其共享方法
公开(公告)号：US20100034043A1
公开(公告)日：2010-02-11
申请号：US12333194
申请日：2008-12-11
申请人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee- Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee- Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/14 , Y10T307/352 , Y10T307/391 , Y10T307/50 , Y10T307/505 , Y10T307/549 , Y10T307/555 , Y10T307/56 , Y10T307/565 , Y10T307/571 , Y10T307/576 , Y10T307/582 , Y10T307/587 , Y10T307/593
摘要： A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.
摘要翻译：能够进行功率共享的半导体IC器件包括被配置为被提供第一电力的第一电力线，被配置为被提供第二电力的第二电力线，被配置为将第一电力线与第二电力连接的开关块响应于第一控制信号的线路;以及功率共享控制块，被配置为根据多个操作命令信号产生控制信号。

18. 发明申请

US20090257301A1 Voltage Level Comparison Circuit of Semiconductor Memory Apparatus, Voltage Adjustment Circuit Using Voltage Level Comparison Circuit, and Semiconductor Memory Apparatus Using the Same 失效
标题翻译：半导体存储器件的电压电平比较电路，使用电压电平比较电路的电压调节电路和使用其的半导体存储器件
公开(公告)号：US20090257301A1
公开(公告)日：2009-10-15
申请号：US12336423
申请日：2008-12-16
申请人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.
摘要翻译：半导体存储装置的电压调整电路包括：控制电压生成部，其被配置为响应于控制信号分配用于选择性地输出多个分配电压的外部电压作为控制电压，所述多个分配电压各自具有不同的电压电平，比较单元，被配置为包括电压供应单元，其被配置为响应于所述电平的电平而控制提供给第一节点的外部电压和第二节点，如果输出电压的电平高于参考电压的电平以及检测信号生成单元，被配置为根据输出电压和参考电压的电平来降低第一和第二节点的电位电平，并输出第二节点的电位电平作为检测信号，以及电压产生单元，被配置为根据检测信号的电位来驱动外部电压并输出外部电压作为输出电压。

19. 发明申请

US20090212853A1 APPARATUS FOR SUPPLYING POWER IN SEMICONDUCTOR INTEGRATED CIRCUIT AND INPUT IMPEDANCE CONTROL METHOD OF THE SAME 审中-公开
标题翻译：用于在半导体集成电路中供电的装置及其输入阻抗控制方法
公开(公告)号：US20090212853A1
公开(公告)日：2009-08-27
申请号：US12347318
申请日：2008-12-31
申请人： Hyung-Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Jae Min Jang , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
发明人： Hyung-Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Jae Min Jang , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
IPC分类号： G05F1/10 , H01L27/00
CPC分类号： H01L27/0727 , H01L29/94
摘要： An apparatus for supplying power in a semiconductor integrated circuit includes a plurality of power lines, each supplying external power to an interior of the semiconductor integrated circuit, and at least one decoupling capacitor set connected to the plurality of power lines and having a resistance value configured to be variable according to a bias voltage.
摘要翻译：一种用于在半导体集成电路中供电的装置包括多个电源线，每个电源线向半导体集成电路的内部提供外部电力，以及至少一个去耦电容器组，连接到多个电力线并具有电阻值配置根据偏置电压可变。

20. 发明申请

US20090128192A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME 失效
标题翻译：半导体集成电路的数据接收器及其控制方法
公开(公告)号：US20090128192A1
公开(公告)日：2009-05-21
申请号：US12176215
申请日：2008-07-18
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： G11C7/00 , H03K19/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver of a semiconductor integrated circuit includes an amplifier that outputs an amplified signal by detecting and amplifying received data using equalization function according to feedback data, a detecting unit that detects a period when data is not received in the amplifier and outputs a detecting signal, and an equalization function control unit that stops the equalization function of the amplifier in response to the detecting signal.
摘要翻译：半导体集成电路的数据接收器包括：放大器，其通过根据反馈数据使用均衡功能检测和放大接收数据来输出放大信号;检测单元，其检测在放大器中未接收到数据的周期，并输出检测信号以及均衡功能控制单元，其响应于检测信号停止放大器的均衡功能。

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