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11. 发明授权

US07782579B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07782579B2
公开(公告)日：2010-08-24
申请号：US11838915
申请日：2007-08-15
申请人： Katsuhiro Kato
发明人： Katsuhiro Kato
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L29/0692 , H01L29/7322
摘要： A semiconductor integrated circuit has a bipolar transistor whose collector is connected to a substrate of an NMOS transistor serving as a protecting transistor. When an ESD event occurs, the bipolar transistor causes the NMOS transistor to be changed into bipolar operation at a low voltage, by supplying current to the substrate of the NMOS transistor. In accordance with this structure, good levels of ESD protecting performance and off leak current of the protecting transistor can both be achieved in the semiconductor integrated circuit.
摘要翻译：半导体集成电路具有双极晶体管，其集电极连接到用作保护晶体管的NMOS晶体管的衬底。当ESD事件发生时，双极晶体管通过向NMOS晶体管的衬底提供电流使NMOS晶体管变为低电压的双极性工作。根据该结构，可以在半导体集成电路中实现保护晶体管的ESD保护性能和漏电流的良好水平。

12. 发明授权

US07545618B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07545618B2
公开(公告)日：2009-06-09
申请号：US11279570
申请日：2006-04-13
申请人： Katsuhiro Kato
发明人： Katsuhiro Kato
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： A semiconductor device includes one or more first transistors of which each source connects to a power wiring, a second transistor of which a source connects to a ground wiring and a drain connects to a drain of the first transistor, one or more third transistors of which each source connects to the power wiring and each drain connects to the drains of the first and second transistors, and a gate potential control circuit which controls the gate potential of the third transistors based on the potential of the power wiring.
摘要翻译：半导体器件包括一个或多个第一晶体管，每个源极连接到电源布线，第二晶体管的源极连接到接地布线，漏极连接到第一晶体管的漏极，一个或多个第三晶体管每个源极连接到电源线，并且每个漏极连接到第一和第二晶体管的漏极;以及栅极电位控制电路，其基于电力布线的电位来控制第三晶体管的栅极电位。

13. 发明申请

US20090078967A1 SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE HAVING A PLURALITY OF SEMICONDUCTOR CHIPS 有权
标题翻译：半导体芯片和具有多个半导体芯片的半导体器件
公开(公告)号：US20090078967A1
公开(公告)日：2009-03-26
申请号：US12193874
申请日：2008-08-19
申请人： Katsuhiro Kato
发明人： Katsuhiro Kato
IPC分类号： H01L27/10
CPC分类号： H01L23/50 , H01L23/60 , H01L25/065 , H01L2224/48227 , H01L2924/13091 , H01L2924/00
摘要： The present invention comprises a semiconductor chip, and a semiconductor device having a plurality of semiconductor chips, that enables ESD protection from another semiconductor chip without increasing the chip area in case the semiconductor chip is Multi-Chip-Packaged, without wasting chip area in case the semiconductor chip is not Multi-Chip-Packaged. The exemplary semiconductor chip of the present invention includes an internal circuit and a first electrode pad electrically connected to a ground bus line of the first semiconductor chip in a region where an electrode pad, which gives and receives electric signals required for an operation of the internal circuit, cannot be provided.
摘要翻译：本发明包括半导体芯片和具有多个半导体芯片的半导体器件，其在半导体芯片是多芯片封装的情况下不会增加芯片面积而能够从另一半导体芯片ESD保护，而不浪费芯片面积半导体芯片不是多芯片封装的。本发明的示例性半导体芯片包括内部电路和电连接到第一半导体芯片的接地总线的第一电极焊盘，其中电极焊盘提供并接收内部操作所需的电信号的区域电路，不能提供。

14. 发明申请

US20080062599A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20080062599A1
公开(公告)日：2008-03-13
申请号：US11838915
申请日：2007-08-15
申请人： Katsuhiro Kato
发明人： Katsuhiro Kato
IPC分类号： H01H9/00
CPC分类号： H01L27/0266 , H01L29/0692 , H01L29/7322
摘要： A semiconductor integrated circuit has a bipolar transistor whose collector is connected to a substrate of an NMOS transistor serving as a protecting transistor. When an ESD event occurs, the bipolar transistor causes the NMOS transistor to be changed into bipolar operation at a low voltage, by supplying current to the substrate of the NMOS transistor. In accordance with this structure, good levels of ESD protecting performance and off leak current of the protecting transistor can both be achieved in the semiconductor integrated circuit.
摘要翻译：半导体集成电路具有双极晶体管，其集电极连接到用作保护晶体管的NMOS晶体管的衬底。当ESD事件发生时，双极晶体管通过向NMOS晶体管的衬底提供电流使NMOS晶体管变为低电压的双极性工作。根据该结构，可以在半导体集成电路中实现保护晶体管的ESD保护性能和漏电流的良好水平。

15. 发明授权

US5962902A Semiconductor CMOS device with circuit for preventing latch-up 失效
标题翻译：具有防止闭锁电路的半导体CMOS器件
公开(公告)号：US5962902A
公开(公告)日：1999-10-05
申请号：US915325
申请日：1997-08-20
申请人： Katsuhiro Kato , Hidekazu Kikuchi
发明人： Katsuhiro Kato , Hidekazu Kikuchi
IPC分类号： G11C11/34 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/04 , H01L27/092 , H02H3/20
CPC分类号： H01L27/0218 , H01L27/0921
摘要： A semiconductor device has a substrate bias generating circuit for generating a substrate bias to be applied to a p-type semiconductor substrate, a CMOS circuit formed on the semiconductor substrate, and a latch-up protection circuit. The latch-up protection circuit has an n-type first region, a highly doped n-type second region, a p-type third region apart from the second region, in the first region and an n-type fourth region surrounding said first region formed apart from the first region on the surface of the substrate. The second region is coupled with a power supply Vcc, the third region is coupled with an input line, the fourth region is coupled with a ground Vss, and the substrate is coupled with the substrate bias generating circuit.
摘要翻译：半导体器件具有用于产生施加到p型半导体衬底的衬底偏置的衬底偏置产生电路，形成在半导体衬底上的CMOS电路和闩锁保护电路。闩锁保护电路在第一区域中具有n型第一区域，高掺杂n型第二区域，与第二区域相距的p型第三区域和围绕所述第一区域的n型第四区域与衬底表面上的第一区域分开形成。第二区域与电源Vcc耦合，第三区域与输入线耦合，第四区域与接地Vss耦合，并且衬底与衬底偏置产生电路耦合。

16. 发明授权

US4452861A Solid particles encapsulated with cyanoacrylate polymer 失效
标题翻译：用氰基丙烯酸酯聚合物包裹的固体颗粒
公开(公告)号：US4452861A
公开(公告)日：1984-06-05
申请号：US380285
申请日：1982-05-20
申请人： Fumio Okamoto , Katsuhiro Kato
发明人： Fumio Okamoto , Katsuhiro Kato
IPC分类号： C09K11/02 , B32B15/08 , B05D5/06
CPC分类号： C09K11/025 , Y10T428/256 , Y10T428/2982 , Y10T428/2989 , Y10T428/31935
摘要： Article of manufacture comprises a solid core particle individually encapsulated with a film consisting essentially of alkyl 2-cyanoacrylate polymeric material. The film may be produced in situ by agitating a mixture of core particles having adsorbed water on the surfaces thereof in a nonaqueous liquid containing dissolved alkyl 2-cyanoacrylate monomer, whereby the monomer and adsorbed water react and deposit the film on the surfaces of the particles.
摘要翻译：制造商包括固体核心颗粒，其单独封装有基本上由2-氰基丙烯酸烷基酯聚合物材料组成的膜。可以通过在含有溶解的2-氰基丙烯酸烷基酯单体的非水溶液中搅拌其表面上具有吸附水的核心颗粒的混合物在原位制备膜，由此单体和吸附的水反应并将膜沉积在颗粒的表面上。

17. 发明授权

US08435117B2 Game device, control method for game device, program and information memory medium 有权
标题翻译：游戏装置，游戏装置的控制方法，程序和信息存储介质
公开(公告)号：US08435117B2
公开(公告)日：2013-05-07
申请号：US12742613
申请日：2008-11-18
申请人： Katsuhiro Kato , Takashi Hayashi
发明人： Katsuhiro Kato , Takashi Hayashi
IPC分类号： G06F17/00
CPC分类号： A63F13/44 , A63F13/10 , A63F13/12 , A63F13/42 , A63F13/92 , A63F2300/406 , A63F2300/6045 , A63F2300/638
摘要： An image that is changed according to a change of a numerical value is displayed. A first numerical value changing section changes the numerical value between a first predetermined value and a second predetermined value. A first input value is acquired based on the numerical value obtained at a time corresponding to a time of a first operation. A second numerical value changing section changes, after the first operation, the numerical value between the numerical value obtained at the time corresponding to the time of the first operation and the second predetermined value. A second input value is acquired based on the numerical value obtained at the time corresponding to the time of the first operation and the numerical value obtained at a time corresponding to a time of a second operation. A game is controlled based on the first input value and the second input value.
摘要翻译：显示根据数值变化而变化的图像。第一数值改变部分改变第一预定值和第二预定值之间的数值。基于在与第一操作的时间相对应的时间获得的数值获取第一输入值。第二数值变更部在第一次操作之后，改变在与第一操作相对应的时刻获得的数值与第二预定值之间的数值。基于在与第一操作的时间相对应的时间获得的数值和在与第二操作的时间相对应的时间获得的数值获得的第二输入值。基于第一输入值和第二输入值来控制游戏。

18. 发明授权

US07791148B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07791148B2
公开(公告)日：2010-09-07
申请号：US11624656
申请日：2007-01-18
申请人： Katsuhiro Kato , Kenji Ichikawa
发明人： Katsuhiro Kato , Kenji Ichikawa
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0619 , H01L27/0266
摘要： A semiconductor device includes a transistor region, a first guard ring, a second guard ring, and a silicide region. A first-conductive-type transistor is formed in the transistor region. The first guard ring is a second-conductive-type first impurity diffusion layer surrounding the transistor region with a first width, and is coupled to a first reference potential. The second guard ring is a first-conductive-type transistor second impurity diffusion layer surrounding the first guard ring with a second width. The silicide region is formed on the surface of the second guard ring such that substantially no silicide is formed on a portion of the surface of the second guard ring on the side facing a drain region of the first-conductive-type transistor, and is connected to a second reference potential line whose potential is higher than that of the first reference potential line.
摘要翻译：半导体器件包括晶体管区域，第一保护环，第二保护环和硅化物区域。第一导电型晶体管形成在晶体管区域中。第一保护环是围绕具有第一宽度的晶体管区域并且耦合到第一参考电位的第二导电型第一杂质扩散层。第二保护环是围绕具有第二宽度的第一保护环的第一导电型晶体管第二杂质扩散层。硅化物区域形成在第二保护环的表面上，使得在与第一导电型晶体管的漏极区域相对的一侧的第二保护环的表面的一部分上基本上不形成硅化物，并且连接到第二参考电位线，其电位高于第一参考电位线的电位。

19. 发明申请

US20070230074A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070230074A1
公开(公告)日：2007-10-04
申请号：US11730081
申请日：2007-03-29
申请人： Katsuhiro Kato
发明人： Katsuhiro Kato
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L29/41725 , H01L29/4238 , H01L29/456 , H01L29/78
摘要： The present invention provides a semiconductor device capable of preventing an electrostatic surge without increasing a leak current. In the semiconductor device, a protection circuit for protecting an internal circuit is provided between a source line and a ground line. The protection circuit has a protection transistor of which the drain is connected to the source line and the source and gate are connected to the ground line. The protection transistor is configured by integrally forming two types of transistor structural portions. The latter of the transistor structural portions is longer than the former thereof in gate length. In addition, the sum of gate widths of the latter transistor structural portions is larger than the sum of gate widths of the former transistor structural portions.
摘要翻译：本发明提供能够防止静电浪涌而不增加泄漏电流的半导体器件。在半导体器件中，在源极线和接地线之间设置有用于保护内部电路的保护电路。保护电路具有保护晶体管，漏极连接到源极线，源极和栅极连接到地线。保护晶体管通过一体地形成两种晶体管结构部分而构成。晶体管结构部分中的后者在栅极长度上比其前者长。此外，后一晶体管结构部分的栅极宽度之和大于前一晶体管结构部分的栅极宽度之和。

20. 发明申请

US20070096793A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070096793A1
公开(公告)日：2007-05-03
申请号：US11469907
申请日：2006-09-05
申请人： Katsuhiro Kato , Kenji Ichikawa , Atsushi Nagayama
发明人： Katsuhiro Kato , Kenji Ichikawa , Atsushi Nagayama
IPC分类号： H03H11/40
CPC分类号： H03K19/00315 , H01L27/0266
摘要： A semiconductor device includes first and second lines, a first transistor configured to electrically connect with the second line, and a second transistor configured to electrically connect the first line and the first transistor, the second transistor being turned ON when a bias voltage for operation is impressed between the first and second lines.
摘要翻译：半导体器件包括第一和第二线，被配置为与第二线电连接的第一晶体管和被配置为电连接第一线和第一晶体管的第二晶体管，当操作偏置电压为第二晶体管时，第二晶体管导通印在第一和第二行之间。

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