会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 13. 发明授权
    • Energy saving capacitance type measuring device for absolute measurement
of positions
    • 用于绝对测量位置的节能电容型测量装置
    • US5440501A
    • 1995-08-08
    • US74952
    • 1993-06-10
    • Toshitaka ShimomuraSatoshi AdachiToru YakuTatsuhiko MatsuuraOsamu Kawatoko
    • Toshitaka ShimomuraSatoshi AdachiToru YakuTatsuhiko MatsuuraOsamu Kawatoko
    • G01D5/241G01B3/20G01B3/18
    • G01D5/2415
    • A capacitance-type measuring device for absolute measurement of positions is disclosed, which comprises a displacement sensor having a fixed element and a movable element, the movable element being capacitance-coupled to the fixed element and relatively movable against the fixed element, the displacement sensor being adapted to output signals corresponding to relative positions of the movable element against the fixed element, a signal processing circuit for processing the output signals of the displacement sensor and outputting an absolute measurement value corresponding to displacement of the movable element against the fixed element, a control circuit for controlling the operations of the displacement sensor and the signal processing circuit, and a power supply for supplying electric power to the displacement sensor, the signal processing circuit, and the control circuit, wherein the control circuit activates the signal processing circuit at a suitable interval so as to perform an intermittent measurement operation.
    • 公开了一种用于绝对测量位置的电容型测量装置,其包括具有固定元件和可移动元件的位移传感器,该可移动元件电容耦合到固定元件并相对于固定元件相对移动,位移传感器 适于将对应于可移动元件相对于固定元件的相对位置的信号输出;信号处理电路,用于处理位移传感器的输出信号,并输出对应于可移动元件相对于固定元件的位移的绝对测量值; 用于控制位移传感器和信号处理电路的操作的控制电路,以及用于向位移传感器,信号处理电路和控制电路供电的电源,其中控制电路在信号处理电路 适当的间隔,以便执行i 不间断的测量操作。
    • 15. 发明授权
    • Capacitance type displacement detection apparatus and method of manufacturing the same
    • 电容式位移检测装置及其制造方法
    • US06538457B2
    • 2003-03-25
    • US09761842
    • 2001-01-18
    • Kenichi NakayamaSatoshi Adachi
    • Kenichi NakayamaSatoshi Adachi
    • G01R2726
    • G01D5/2415
    • Both a sensor portion and a signal processing portion are provided on a glass board. The sensor portion is formed by subjecting a conductive layer to the patterning process. A gold coupling layer is provided on the conductive layer and the signal processing portion is formed by the flip chip method on the coupling layer. The sensor portion and the signal processing portion may be formed on the major surface and the rear surface of the glass board and these portions may be coupled by through holes. Since the signal processing portion as well as the sensor portion is formed on the glass board, the wiring distance can be made shorter and the entire size of the sensor can be miniaturized.
    • 传感器部分和信号处理部分均设置在玻璃板上。 传感器部分通过对导电层进行图案化处理而形成。 在导电层上设置金结合层,在耦合层上通过倒装芯片法形成信号处理部分。 传感器部分和信号处理部分可以形成在玻璃板的主表面和后表面上,并且这些部分可以通过通孔联接。 由于信号处理部分和传感器部分形成在玻璃板上,所以布线距离可以缩短,并且传感器的整体尺寸可以小型化。
    • 16. 发明授权
    • Code translation circuit for converting a binary data to a binary coded
decimal data
    • 用于将二进制数据转换为二进制编码的十进制数据的代码转换电路
    • US5982307A
    • 1999-11-09
    • US891642
    • 1997-07-11
    • Satoshi Adachi
    • Satoshi Adachi
    • G06F5/00H03M7/12
    • H03M7/12
    • The first shift-register 1 has 4 bits.times.N stages for storing the operated result BCD data 4 bits by 4 bits from LSD. The second shift-register 2 has 4 bits.times.M stages for storing a BIN data to be translated 4 bits by 4 bits from MSD. The D-F/F 5 is to store the output from the first shift-register 1 and the intermediate result, and output thereof is supplied to the arithmetic/logic circuit 6 through the first selector 3. The output of the second shift-register 2 is selected by the second selector 4 to be supplied to the arithmetic/logic circuit 6. The arithmetic/logic circuit 6 performs.times.16 operation for the stored data in the shift register 1, and adding the resultant to 4 bits data stored in the shift-register 2 with carry process. The output DO of the arithmetic/logic circuit 6 is stored in the D-F/F 5 in the first half of the shift clock SCK1, and stored in the shift-register 1 in the latter half of the shift clock SCK1. The shift-register 1 makes a round, while the shift-register 2 is 1 stage shifted.
    • 第一移位寄存器1具有4位×N级,用于将操作结果BCD数据4位从LSD存储4位。 第二移位寄存器2具有4位×M级,用于存储要从MSD 4位×4位转换的BIN数据。 DF / F 5存储来自第一移位寄存器1的输出和中间结果,其输出通过第一选择器3提供给运算逻辑电路6.第二移位寄存器2的输出为 算术/逻辑电路6对移位寄存器1中存储的数据执行x16操作,并将结果相加于存储在移位寄存器2中的4位数据 随身携带。 算术/逻辑电路6的输出DO存储在移位时钟SCK1的前半部分的D-F / F 5中,并存储在移位时钟SCK1的后半部分的移位寄存器1中。 移位寄存器1进行回合,而移位寄存器2为1级位移。