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11. 发明申请

US20070286273A1 Circuit and Method for Pulse Width Modulation by Means of Synchronized, Self-Oscillating Pulse Width Modulators 有权
标题翻译：通过同步，自振荡脉宽调制器进行脉宽调制的电路和方法
公开(公告)号：US20070286273A1
公开(公告)日：2007-12-13
申请号：US11760066
申请日：2007-06-08
申请人： Martin Clara , Andreas Wiesbauer , Thomas Poetscher , David San Segundo Bello , Sergio Walter
发明人： Martin Clara , Andreas Wiesbauer , Thomas Poetscher , David San Segundo Bello , Sergio Walter
IPC分类号： H03K7/08 , H03K9/08
CPC分类号： H03K7/08 , H03F3/217 , H03F2200/351
摘要： A pulse width modulator circuit has two self-oscillating pulse width modulators and a synchronization circuit for synchronizing the two self-oscillating pulse width modulators. It also comprises an auxiliary-signal generating circuit for generating an auxiliary signal which is coupled into the two self-oscillating pulse width modulators.
摘要翻译：脉宽调制器电路具有两个自振荡脉宽调制器和同步两个自振荡脉宽调制器的同步电路。它还包括辅助信号发生电路，用于产生耦合到两个自振荡脉冲宽度调制器中的辅助信号。

12. 发明授权

US07199741B2 Method for digital/analog conversion and corresponding digital/analog converter device 有权
标题翻译：数字/模拟转换方法及相应的数/模转换器装置
公开(公告)号：US07199741B2
公开(公告)日：2007-04-03
申请号：US10971570
申请日：2004-10-22
申请人： Martin Clara , Wolfgang Klatzer , Andreas Wiesbauer
发明人： Martin Clara , Wolfgang Klatzer , Andreas Wiesbauer
IPC分类号： H03M1/66
CPC分类号： H03M1/0678 , H03M1/0665 , H03M1/747 , H03M3/464
摘要： A method and a device for digital/analog conversion are proposed, whereby for improved use of a “dynamic element matching” algorithm, in particular a “data weighted averaging” algorithm, the number of existing conversion elements is greater than a maximum number of possible input or control codes for the conversion elements (7), that is to say greater than a number of conversion elements, which would actually be necessary for a maximum value of the digital word to be converted in each case.
摘要翻译：提出了一种用于数字/模拟转换的方法和装置，其中为了改进使用“动态元件匹配”算法，特别是“数据加权平均”算法，现有转换元件的数量大于可能的最大数量用于转换元件（7）的输入或控制代码，也就是说大于转换元件的数量，这在每种情况下实际上对于要转换的数字字的最大值是必需的。

13. 发明授权

US07928800B2 Programmable compensation network for operational amplifiers 有权
标题翻译：运算放大器的可编程补偿网络
公开(公告)号：US07928800B2
公开(公告)日：2011-04-19
申请号：US12327739
申请日：2008-12-03
申请人： Fabio Ballarin , Alfonso D'Andretta , Martin Clara , Antonio Di Giandomenico , Dario Giotta , Andreas Wiesbauer
发明人： Fabio Ballarin , Alfonso D'Andretta , Martin Clara , Antonio Di Giandomenico , Dario Giotta , Andreas Wiesbauer
IPC分类号： H03F1/36
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2203/45528
摘要： Systems and methods for implementing a programmable network for a multimode conditionally stable operational amplifier are disclosed.
摘要翻译：公开了用于实现用于多模有条件稳定的运算放大器的可编程网络的系统和方法。

14. 发明授权

US07796072B2 Multiple mode sigma-delta modulator 有权
标题翻译：多模式Σ-Δ调制器
公开(公告)号：US07796072B2
公开(公告)日：2010-09-14
申请号：US12255038
申请日：2008-10-21
申请人： Antonio Di Giandomenico , David San Segundo Bello , Andreas Wiesbauer , Fabio Ballarin , Martin Clara
发明人： Antonio Di Giandomenico , David San Segundo Bello , Andreas Wiesbauer , Fabio Ballarin , Martin Clara
IPC分类号： H03M3/00
CPC分类号： H03M3/386 , H03M3/458
摘要： Modulation circuits for operating in at least a first and second mode are described herein.
摘要翻译：至少在第一和第二模式下操作的调制电路在此描述。

15. 发明授权

US07688236B2 Integrated circuit comprising a plurality of digital-to-analog converters, sigma-delta modulator circuit, and method of calibrating a plurality of multibit digital-to-analog converters 有权
标题翻译：包括多个数模转换器，Σ-Δ调制器电路以及校准多个数模转换器的方法的集成电路
公开(公告)号：US07688236B2
公开(公告)日：2010-03-30
申请号：US11865539
申请日：2007-10-01
申请人： Antonio Di Giandomenico , Martin Clara , David San Segundo Bello , Wolfgang Klatzer , Luca Gori , Andreas Wiesbauer
发明人： Antonio Di Giandomenico , Martin Clara , David San Segundo Bello , Wolfgang Klatzer , Luca Gori , Andreas Wiesbauer
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/742 , H03M3/386 , H03M3/424 , H03M3/454
摘要： In an integrated circuit including a first multibit digital-to-analog converter and a second multibit digital-to-analog converter, a calibration circuit is provided which is shared between the first and second digital-to-analog converters.
摘要翻译：在包括第一多位数模转换器和第二多位数模转换器的集成电路中，提供了在第一和第二数模转换器之间共享的校准电路。

16. 发明申请

US20080297385A1 Sigma-Delta Analog-Digital Converter For An Xdsl Multistandard Input Stage 失效
标题翻译：用于Xdsl多标准输入级的Sigma-Delta模拟数字转换器
公开(公告)号：US20080297385A1
公开(公告)日：2008-12-04
申请号：US11661627
申请日：2004-09-02
申请人： Martin Clara , Antonio Di Giandomenico , Joerg Hauptmann , Andreas Wiesbauer
发明人： Martin Clara , Antonio Di Giandomenico , Joerg Hauptmann , Andreas Wiesbauer
IPC分类号： H03M3/04
CPC分类号： H03M3/394 , H03M3/406 , H03M3/424 , H03M3/452
摘要： The invention relates to a sigma-delta analogue/digital converter for an xDSL multi-standard input stage for converting an xDSL signal into a digital output signal, where the sigma-delta analogue/digital converter (1) has: an analogue loop filter (6) which filters an analogue difference signal between the xDSL signal to be converted and a feedback signal in order to produce a filter output signal; a quantizer which quantizes the filter output signal from the analogue loop filter (6) in order to produce the digital output signal; a first digital/analogue converter (16) which converts the digital output signal into the analogue feedback signal; where the analogue loop filter (6) has at least two resonator filter stages (6a, 6b) which respectively comprise a first integrator (6a-1; 6b-1) and a second integrator (6a-2; 6b-2) connected in series therewith, where the second integrator (6a-2; 6b-2) can be connected to the first integrator (6a-1, 6b-1) by means of a controllable feedback switch (6a-3, 6b-3) in order to close a local feedback loop, where the integrator outputs can respectively be connected by means of a controllable switch (25) to a signal input of an adder (27) which adds the output signals from the integrators in order to produce the filter output signal.
摘要翻译：本发明涉及一种用于xDSL多标准输入级的Σ-Δ模拟/数字转换器，用于将xDSL信号转换成数字输出信号，其中Σ-Δ模拟/数字转换器（1）具有：模拟环路滤波器 6），其对要转换的xDSL信号和反馈信号之间的模拟差分信号进行滤波，以产生滤波器输出信号; 量化器，其量化来自模拟环路滤波器（6）的滤波器输出信号，以产生数字输出信号; 第一数字/模拟转换器（16），其将数字输出信号转换成模拟反馈信号; 其中模拟环路滤波器（6）具有至少两个分别包括第一积分器（6a-1; 6b-1）和第二积分器（6a-2; 6b-2）的谐振器滤波器级（6a，6b）其中第二积分器（6a-2; 6b-2）可以通过可控反馈开关（6a-3,6b-3）按顺序连接到第一积分器（6a-1,6b-1）以闭合局部反馈回路，其中积分器输出可以分别通过可控开关（25）连接到加法器（27）的信号输入端，加法器（27）的信号输入相加来自积分器的输出信号，以产生滤波器输出信号。

17. 发明授权

US07262723B2 Compensation circuit for clock jitter compensation 有权
标题翻译：时钟抖动补偿补偿电路
公开(公告)号：US07262723B2
公开(公告)日：2007-08-28
申请号：US11451229
申请日：2006-06-12
申请人： Dietmar Straussnig , Bernd Rainer , Andreas Wiesbauer , Richard Gaggl , Martin Clara , Luis Hernandez
发明人： Dietmar Straussnig , Bernd Rainer , Andreas Wiesbauer , Richard Gaggl , Martin Clara , Luis Hernandez
IPC分类号： H03M1/10
CPC分类号： H03M1/0836 , H03M1/66
摘要： A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.
摘要翻译：一种用于数/模转换器的补偿电路，其由包括抖动的时钟信号计时，并将数字输入数据信号转换成包括由于所述抖动引起的抖动误差的模拟输出数据信号，包括用于测量抖动的测量电路以及用于产生数字建模的抖动误差信号的建模电路，其根据所测量的抖动和数字输入数据信号模拟抖动误差，其中从数字输入数据信号中减去数字建模的抖动误差信号。

18. 发明申请

US20070104266A1 Synchronization circuit for synchronizing PWM modulators 有权
标题翻译：用于同步PWM调制器的同步电路
公开(公告)号：US20070104266A1
公开(公告)日：2007-05-10
申请号：US11593235
申请日：2006-11-06
申请人： Martin Clara , Thomas Poetscher , Sergio Walter , Andreas Wiesbauer
发明人： Martin Clara , Thomas Poetscher , Sergio Walter , Andreas Wiesbauer
IPC分类号： H03K7/08 , H04L7/06
CPC分类号： H03K7/08 , H03F3/2173 , H03K5/135
摘要： A synchronization circuit for synchronizing at least two self-oscillating PWM modulators, each outputting a respective pulse-width-modulated output signal comprising signal pulses with signal pulse centers, shifts the timings of the signal pulses relative to one another such that their signal pulse centers are in sync.
摘要翻译：同步电路，用于同步至少两个自激振荡PWM调制器，每个自振荡PWM调制器输出包括具有信号脉冲中心的信号脉冲的相应的脉冲宽度调制输出信号，使信号脉冲相对于彼此的定时偏移，使得它们的信号脉冲中心正在同步

19. 发明申请

US20070057830A1 Apparatus and method for spectrally shaping a reference clock signal 有权
标题翻译：对参考时钟信号进行频谱整形的装置和方法
公开(公告)号：US20070057830A1
公开(公告)日：2007-03-15
申请号：US11516383
申请日：2006-09-06
申请人： Andreas Wiesbauer , Luis Hernandez , Dietmar Straussnigg , Daniel Gruber , Richard Gaggl , Martin Clara , Stefan Matschitsch
发明人： Andreas Wiesbauer , Luis Hernandez , Dietmar Straussnigg , Daniel Gruber , Richard Gaggl , Martin Clara , Stefan Matschitsch
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , H03L7/18 , H03M3/372 , H03M3/464
摘要： Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).
摘要翻译：用于检测参考时钟信号（CLK）中的时钟信号抖动的时钟信号抖动检测电路，具有由参考时钟信号（CLK）计时的开关电容器参考数模转换器（15），并转换数字输入信号转换为第一电流，电流控制的数模转换器（16），其由参考时钟信号（CLK）计时，并将数字输入信号转换为第二电流，并具有积分器（18）第一电流和第二电流之间的差异，以产生指示参考时钟信号（CLK）中的时钟信号抖动的信号。

20. 发明授权

US06989778B2 Semi-conductor circuit arrangement 有权
标题翻译：半导体电路布置
公开(公告)号：US06989778B2
公开(公告)日：2006-01-24
申请号：US10938741
申请日：2004-09-10
申请人： Martin Clara , Antonio Di Giandomenico , Andreas Wiesbauer
发明人： Martin Clara , Antonio Di Giandomenico , Andreas Wiesbauer
IPC分类号： H03M3/00
CPC分类号： H03M3/39 , H03M3/424 , H03M3/452 , H03M3/454
摘要： A semi-conductor circuit arrangement for a continuous time sigma delta modulator for adding analog input signals to a digital fed back signal and for quantizing the totalled signal comprises a voltage to current conversion circuit (10), an adding circuit (20) with a resistor ladder, a quantizing circuit (40) with comparator elements (45) and a digital to analog conversion circuit (30). For each comparator element (45) its respective input signal is formed by a voltage which is released between a tap in front of a corresponding tapping resistor (22) in a first string of the resistor ladder and a tap in front of a corresponding tapping resistor (22) in a second string of the resistor ladder.
摘要翻译：一种用于将模拟输入信号加到数字反馈信号并用于量化总计信号的连续时间Σ-Δ调制器的半导体电路装置包括电压 - 电流转换电路（10），具有电阻的加法电路（20）梯形图，具有比较器元件（45）和数模转换电路（30）的量化电路（40）。对于每个比较器元件（45），其相应的输入信号由在电阻梯的第一串中的对应的分接电阻器（22）前面的抽头和相应的分接电阻器前面的抽头之间的抽头释放的电压形成（22）在电阻梯的第二串中。

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