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1. 发明申请

US20070057830A1 Apparatus and method for spectrally shaping a reference clock signal 有权
标题翻译：对参考时钟信号进行频谱整形的装置和方法
公开(公告)号：US20070057830A1
公开(公告)日：2007-03-15
申请号：US11516383
申请日：2006-09-06
申请人： Andreas Wiesbauer , Luis Hernandez , Dietmar Straussnigg , Daniel Gruber , Richard Gaggl , Martin Clara , Stefan Matschitsch
发明人： Andreas Wiesbauer , Luis Hernandez , Dietmar Straussnigg , Daniel Gruber , Richard Gaggl , Martin Clara , Stefan Matschitsch
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , H03L7/18 , H03M3/372 , H03M3/464
摘要： Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).
摘要翻译：用于检测参考时钟信号（CLK）中的时钟信号抖动的时钟信号抖动检测电路，具有由参考时钟信号（CLK）计时的开关电容器参考数模转换器（15），并转换数字输入信号转换为第一电流，电流控制的数模转换器（16），其由参考时钟信号（CLK）计时，并将数字输入信号转换为第二电流，并具有积分器（18）第一电流和第二电流之间的差异，以产生指示参考时钟信号（CLK）中的时钟信号抖动的信号。

2. 发明授权

US07379005B2 Apparatus and method for spectrally shaping a reference clock signal 有权
标题翻译：对参考时钟信号进行频谱整形的装置和方法
公开(公告)号：US07379005B2
公开(公告)日：2008-05-27
申请号：US11516383
申请日：2006-09-06
申请人： Andreas Wiesbauer , Luis Hernandez , Dietmar Sträussnigg , Daniel Gruber , Richard Gaggl , Martin Clara , Stefan Matschitsch
发明人： Andreas Wiesbauer , Luis Hernandez , Dietmar Sträussnigg , Daniel Gruber , Richard Gaggl , Martin Clara , Stefan Matschitsch
IPC分类号： H03M1/66
CPC分类号： H03L7/08 , H03L7/18 , H03M3/372 , H03M3/464
摘要： Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).
摘要翻译：用于检测参考时钟信号（CLK）中的时钟信号抖动的时钟信号抖动检测电路，具有由参考时钟信号（CLK）计时的开关电容器参考数模转换器（15），并转换数字输入信号转换为第一电流，电流控制的数模转换器（16），其由参考时钟信号（CLK）计时，并将数字输入信号转换为第二电流，并具有积分器（18）第一电流和第二电流之间的差异，以产生指示参考时钟信号（CLK）中的时钟信号抖动的信号。

3. 发明授权

US07262723B2 Compensation circuit for clock jitter compensation 有权
标题翻译：时钟抖动补偿补偿电路
公开(公告)号：US07262723B2
公开(公告)日：2007-08-28
申请号：US11451229
申请日：2006-06-12
申请人： Dietmar Straussnig , Bernd Rainer , Andreas Wiesbauer , Richard Gaggl , Martin Clara , Luis Hernandez
发明人： Dietmar Straussnig , Bernd Rainer , Andreas Wiesbauer , Richard Gaggl , Martin Clara , Luis Hernandez
IPC分类号： H03M1/10
CPC分类号： H03M1/0836 , H03M1/66
摘要： A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.
摘要翻译：一种用于数/模转换器的补偿电路，其由包括抖动的时钟信号计时，并将数字输入数据信号转换成包括由于所述抖动引起的抖动误差的模拟输出数据信号，包括用于测量抖动的测量电路以及用于产生数字建模的抖动误差信号的建模电路，其根据所测量的抖动和数字输入数据信号模拟抖动误差，其中从数字输入数据信号中减去数字建模的抖动误差信号。

4. 发明申请

US20060279441A1 Compensation circuit for clock jitter compensation 有权
标题翻译：时钟抖动补偿补偿电路
公开(公告)号：US20060279441A1
公开(公告)日：2006-12-14
申请号：US11451229
申请日：2006-06-12
申请人： Dietmar Straussnig , Bernd Rainer , Andreas Wiesbauer , Richard Gaggl , Martin Clara , Luis Hernandez
发明人： Dietmar Straussnig , Bernd Rainer , Andreas Wiesbauer , Richard Gaggl , Martin Clara , Luis Hernandez
IPC分类号： H03M1/06
CPC分类号： H03M1/0836 , H03M1/66
摘要： A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.
摘要翻译：一种用于数/模转换器的补偿电路，其由包括抖动的时钟信号计时，并将数字输入数据信号转换成包括由于所述抖动引起的抖动误差的模拟输出数据信号，包括用于测量抖动的测量电路以及用于产生数字建模的抖动误差信号的建模电路，其根据所测量的抖动和数字输入数据信号模拟抖动误差，其中从数字输入数据信号中减去数字建模的抖动误差信号。

5. 发明授权

US07333041B2 System for analog-to-digital conversion 有权
标题翻译：用于模数转换的系统
公开(公告)号：US07333041B2
公开(公告)日：2008-02-19
申请号：US11471458
申请日：2006-06-20
申请人： Richard Gaggl , Dietmar Straussnigg , Andreas Wiesbauer
发明人： Richard Gaggl , Dietmar Straussnigg , Andreas Wiesbauer
IPC分类号： H03M3/00
CPC分类号： H03M3/492 , H03M3/436 , H03M3/48
摘要： An analog-to-digital converter system converts an analog input signal into a digital output signal. The analog input signal is converted into a first digital signal by a fed back analog-to-digital conversion. A second digital signal is additionally formed, depending on the analog input signal or on the digital output signal, which, combined with the first digital signal, results in the digital output signal.
摘要翻译：模拟 - 数字转换器系统将模拟输入信号转换为数字输出信号。模拟输入信号通过反馈模数转换转换为第一数字信号。根据模拟输入信号或数字输出信号，另外形成第二数字信号，其与第一数字信号结合，产生数字输出信号。

6. 发明申请

US20070013570A1 System for analog-to-digital conversion 有权
标题翻译：用于模数转换的系统
公开(公告)号：US20070013570A1
公开(公告)日：2007-01-18
申请号：US11471458
申请日：2006-06-20
申请人： Richard Gaggl , Dietmar Straussnigg , Andreas Wiesbauer
发明人： Richard Gaggl , Dietmar Straussnigg , Andreas Wiesbauer
IPC分类号： H03M1/12
CPC分类号： H03M3/492 , H03M3/436 , H03M3/48
摘要： An analog-to-digital converter system converts an analog input signal into a digital output signal. The analog input signal is converted into a first digital signal by a fed back analog-to-digital conversion. A second digital signal is additionally formed, depending on the analog input signal or on the digital output signal, which, combined with the first digital signal, results in the digital output signal.
摘要翻译：模拟 - 数字转换器系统将模拟输入信号转换为数字输出信号。模拟输入信号通过反馈模数转换转换为第一数字信号。根据模拟输入信号或数字输出信号，另外形成第二数字信号，其与第一数字信号结合，产生数字输出信号。

7. 发明授权

US07002404B2 Tuning circuit for a filter 有权
标题翻译：滤波器调谐电路
公开(公告)号：US07002404B2
公开(公告)日：2006-02-21
申请号：US10773710
申请日：2004-02-06
申请人： Richard Gaggl , Manfred Nopp , Peter Pessl , Christian Schranz , Dietmar Straussnigg
发明人： Richard Gaggl , Manfred Nopp , Peter Pessl , Christian Schranz , Dietmar Straussnigg
IPC分类号： H03K5/00
CPC分类号： H03H11/1291 , H03H19/008 , H03H2210/021 , H03H2210/043
摘要： The invention relates to a tuning circuit for tuning a filter stage, which has an RC element (1) with an RC time constant (τ), with the RC time constant (τ) being the product of the resistance of a resistor (R1) in the RC element (1) and the capacitance of a capacitor (C1), which is connected in series with the resistor (R1), in the RC element (1), having a comparator (10) for comparison of the voltage which is produced at the potential node (4) between the resistor (R1) and the capacitor (C1), with a reference ground voltage; and having a controller (15) which varies the charge on the capacitor (C1) in the RC element (1) until the comparator (10) indicates that the voltage which is produced at the potential node (4) is equal to the reference ground voltage, with the controller (15) switching a capacitor array (26) as a function of the charge variation time, which capacitor array (26) is connected in parallel with the capacitor (C1) in the RC element (1), in order to compensate for any discrepancy between the RC time constant (τ) of the RC element (1) and a nominal value.
摘要翻译：本发明涉及一种用于调谐滤波器级的调谐电路，其具有RC时间常数（τ）的RC元件（1），其中RC时间常数（τ）是电阻器（R 1 ）和RC元件（1）中与电阻器（R 1）串联连接的电容器（C1）的电容，具有比较器（10），用于比较在电阻器（R 1）和电容器（C 1）之间的电位节点（4）产生的具有参考接地电压的电压; 并且具有改变RC元件（1）中的电容器（C1）上的电荷的控制器（15），直到比较器（10）指示在电势节点（4）处产生的电压等于参考接地电压，控制器（15）根据电荷变化时间切换电容器阵列（26），电容器阵列（26）与RC元件（1）中的电容器（C 1）并联连接，以便补偿RC元件（1）的RC时间常数（τ）与标称值之间的任何差异。

8. 发明授权

US07034729B2 Adding circuit suitable for sigma-delta modulator circuits 失效
标题翻译：添加适用于Σ-Δ调制器电路的电路
公开(公告)号：US07034729B2
公开(公告)日：2006-04-25
申请号：US10935675
申请日：2004-09-02
申请人： Richard Gaggl , Maurizio Inversi , Andreas Wiesbauer
发明人： Richard Gaggl , Maurizio Inversi , Andreas Wiesbauer
IPC分类号： H03M3/00
CPC分类号： H03K5/249
摘要： An adding circuit includes storage capacitors and a a switch mechanism, the storage capacitors being charged up via voltage signals to be added during a first clock phase. During a second clock phase, the storage capacitors are connected in parallel, with the result that a charge equalization occurs. After the charge equalization, the voltage dropped across the parallel-connected storage capacitors is equal to a sum of the signals to be added except for a scaling factor. In one embodiment, the adding circuit is used in a sigma-delta modulator circuit.
摘要翻译：加法电路包括存储电容器和开关机构，存储电容器通过在第一时钟相位期间被添加的电压信号而被充电。在第二时钟相位期间，存储电容器并联连接，结果是发生电荷均衡。在电荷均衡之后，并联连接的存储电容器中的电压下降等于除了缩放因子之外要添加的信号的总和。在一个实施例中，加法电路用于Σ-Δ调制器电路。

9. 发明申请

US20050093728A1 Adding circuit suitable for sigma-delta modulator circuits 失效
标题翻译：添加适用于Σ-Δ调制器电路的电路
公开(公告)号：US20050093728A1
公开(公告)日：2005-05-05
申请号：US10935675
申请日：2004-09-02
申请人： Richard Gaggl , Maurizio Inversi , Andreas Wiesbauer
发明人： Richard Gaggl , Maurizio Inversi , Andreas Wiesbauer
IPC分类号： G06F7/50 , H03K5/00 , H03K5/24 , H03K7/00 , H03M3/00 , H03M3/02
CPC分类号： H03K5/249
摘要： An adding circuit is disclosed. The adding circuit includes storage capacitors and switching or switching means, the storage capacitors being charged up via voltage signals to be added during a first clock phase. During a second clock phase, the storage capacitors are connected in parallel, with the result that a charge equalization occurs. After the charge equalization, the voltage dropped across the parallel-connected storage capacitors is equal to a sum of the signals to be added except for a scaling factor. In one embodiment, the adding circuit is used in a sigma-delta modulator circuit.
摘要翻译：公开了一种加法电路。加法电路包括存储电容器和开关或开关装置，存储电容器通过在第一时钟相位期间被加到的电压信号进行充电。在第二时钟相位期间，存储电容器并联连接，结果是发生电荷均衡。在电荷均衡之后，并联连接的存储电容器中的电压下降等于除了缩放因子之外要添加的信号的总和。在一个实施例中，加法电路用于Σ-Δ调制器电路。

10. 发明授权

US07834696B2 Common mode control circuitry for multi-stage operational amplifiers 有权
标题翻译：用于多级运算放大器的共模控制电路
公开(公告)号：US07834696B2
公开(公告)日：2010-11-16
申请号：US12062539
申请日：2008-04-04
申请人： Dario Giotta , Richard Gaggl , Ivonne Di Sancarlo , Andrea Baschirotto
发明人： Dario Giotta , Richard Gaggl , Ivonne Di Sancarlo , Andrea Baschirotto
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/45179 , H03F3/45632 , H03F3/45928 , H03F2203/45008 , H03F2203/45082 , H03F2203/45138 , H03F2203/45366 , H03F2203/45424
摘要： This disclosure relates to a common mode regulation in multi stage differential amplifiers.
摘要翻译：本公开涉及多级差分放大器中的共模调节。

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