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11. 发明申请

US20060277126A1 Ring credit management 审中-公开
标题翻译：戒指信用管理
公开(公告)号：US20060277126A1
公开(公告)日：2006-12-07
申请号：US11145676
申请日：2005-06-06
申请人： Mark Rosenbluth , Sridhar Lakshmanamurthy
发明人： Mark Rosenbluth , Sridhar Lakshmanamurthy
IPC分类号： G06Q40/00
CPC分类号： G06F9/5016 , G06Q40/00
摘要： Techniques that may be utilized in a multiprocessor computing system are described. In one embodiment, a request from a thread includes a credit parameter that may be used to update a credit register of a ring manager.
摘要翻译：描述可以在多处理器计算系统中使用的技术。在一个实施例中，来自线程的请求包括可用于更新环管理器的信用登记器的信用参数。

12. 发明申请

US20060047873A1 Scalable, two-stage round robin arbiter with re-circulation and bounded latency 有权
标题翻译：可扩展的两阶段循环仲裁器具有重新循环和有限延迟
公开(公告)号：US20060047873A1
公开(公告)日：2006-03-02
申请号：US10933621
申请日：2004-09-02
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Alok Mathur
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Alok Mathur
IPC分类号： G06F13/14
CPC分类号： G06F13/4022 , G06F13/362
摘要： A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers. Another embodiment employs re-prioritization of second stage losers.
摘要翻译：可扩展的两阶段循环仲裁器，具有重新循环和有限延迟，可用于多线程多处理器件。实现两级仲裁器的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。底盘互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线。采用两阶段仲裁方案仲裁访问命令总线。第一个仲裁阶段用于在给定群集中由主人发出的命令请求之间进行仲裁。第二仲裁阶段用于在获胜的第一阶段命令请求之间进行仲裁。仲裁方案的一个实施例采用第二阶段输家的再循环。另一个实施例使用第二阶段输家的重新排序。

13. 发明申请

US20060221980A1 Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency 有权
公开(公告)号：US20060221980A1
公开(公告)日：2006-10-05
申请号：US11097067
申请日：2005-03-31
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Suri Medapati , Edwin O'Yang
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Suri Medapati , Edwin O'Yang
IPC分类号： H04L12/56 , H04L12/28 , H04L12/66
CPC分类号： H04L49/101 , H04L49/254
摘要： A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage. Another embodiment employs a complementary rotating priority arbitration scheme at the second stage.

14. 发明申请

US20160019936A1 ULTRA LOW POWER ARCHITECTURE TO SUPPORT ALWAYS ON PATH TO MEMORY 有权
标题翻译：超低功耗体系结构支持始终保持通向存储器
公开(公告)号：US20160019936A1
公开(公告)日：2016-01-21
申请号：US14336128
申请日：2014-07-21
申请人： Suketu R. Partiwala , Prashanth Kalluraya , Bruce L. Fleming , Shreekant S. Thakkar , Kenneth D. Shoemaker , Sridhar Lakshmanamurthy , Sami Yehia , Joydeep Ray
发明人： Suketu R. Partiwala , Prashanth Kalluraya , Bruce L. Fleming , Shreekant S. Thakkar , Kenneth D. Shoemaker , Sridhar Lakshmanamurthy , Sami Yehia , Joydeep Ray
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G06F1/189 , G06F1/26 , G06F1/32 , G06F1/3275 , Y02D10/14
摘要： An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.
摘要翻译：这里描述了具有超低功率结构的装置。该装置包括第一供电轨道，其中多个子系统由第一供电轨道供电。该设备还包括第二电源轨，其中多个自主子系统将由电源轨供电，其中第二电源轨将始终处于开启状态，始终可用且功率低。

15. 发明授权

US08929373B2 Sending packets with expanded headers 有权
标题翻译：发送带扩展报头的数据包
公开(公告)号：US08929373B2
公开(公告)日：2015-01-06
申请号：US13248234
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Rohit R. Verma , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Rohit R. Verma , Robert P. Adler
IPC分类号： H04L12/28 , H04J3/16 , G06F15/78 , H04L29/06
CPC分类号： H04L45/74 , G06F13/4022 , G06F15/7825 , H04L69/22
摘要： In one embodiment, the present invention is directed to method for receiving a packet in a first agent, where the packet includes a first packet header with an expanded header indicator. Based on this indicator, the agent can determine if the packet includes one or more additional packet headers. If so, the agent can next determining if it supports information in the additional packet header based on a header identifier of the additional header. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明涉及用于在第一代理中接收分组的方法，其中所述分组包括具有扩展的报头指示符的第一分组报头。基于该指示符，代理可以确定该分组是否包括一个或多个附加分组报头。如果是，则代理可以基于附加报头的报头标识符来确定是否支持附加分组报头中的信息。描述和要求保护其他实施例。

16. 发明授权

US08805926B2 Common idle state, active state and credit management for an interface 有权
标题翻译：公共空闲状态，接口的活动状态和信用管理
公开(公告)号：US08805926B2
公开(公告)日：2014-08-12
申请号：US13248232
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Robert P. Adler , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
发明人： Sridhar Lakshmanamurthy , Robert P. Adler , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
IPC分类号： G06F15/16
CPC分类号： G06F13/42 , G06F9/466 , G06F15/7825 , G06F15/7864 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes method for entering a credit initialization state of an agent state machine of an agent coupled to a fabric to initialize credits in a transaction credit tracker of the fabric. This tracker tracks credits for transaction queues of a first channel of the agent for a given transaction type. The agent may then assert a credit initialization signal to cause credits to be stored in the transaction credit tracker corresponding to the number of the transaction queues of the first channel of the agent for the first transaction type. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于输入耦合到结构的代理的代理状态机的信用初始化状态以便初始化该结构的交易信用跟踪器中的信用的方法。该跟踪器跟踪给定交易类型的代理的第一渠道的交易队列的信用。然后，代理可以断言信用初始化信号，以使得信用被存储在与第一交易类型的代理的第一渠道的交易队列的数量相对应的交易信用跟踪器中。描述和要求保护其他实施例。

17. 发明申请

US20130086586A1 Issuing Requests To A Fabric 有权
公开(公告)号：US20130086586A1
公开(公告)日：2013-04-04
申请号：US13248276
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
IPC分类号： G06F9/46
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/368 , G06F13/4022 , G06F15/7807 , G06F15/7864
摘要： In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

18. 发明授权

US08087024B2 Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache 失效
标题翻译：具有L1指令高速缓存和共享L2指令高速缓存的多个多线程处理器
公开(公告)号：US08087024B2
公开(公告)日：2011-12-27
申请号：US12313247
申请日：2008-11-18
申请人： Sridhar Lakshmanamurthy , Wilson Y. Liao , Prashant R. Chandra , Jeen-Yuan Miin , Yim Pun
发明人： Sridhar Lakshmanamurthy , Wilson Y. Liao , Prashant R. Chandra , Jeen-Yuan Miin , Yim Pun
IPC分类号： G06F9/46 , G06F13/00 , G06F12/00 , G06F15/76 , G06F9/44
CPC分类号： G06F12/0811 , G06F12/0842 , H04L69/12
摘要： In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.
摘要翻译：一般来说，一方面，本发明描述了一种处理器，其包括指令存储器，用于存储至少一个程序的至少一部分和耦合到共享指令存储器的多个引擎的指令。引擎提供多个执行线程并且包括指令高速缓存以从指令存储器缓存至少一个程序的至少一部分的子集，其中引擎指令高速缓存的不同相应部分分配给引擎的不同相应引擎线程。

19. 发明授权

US07707266B2 Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit 失效
标题翻译：可扩展的，高性能的全球互连方案，用于多线程，多处理系统级芯片网络处理器单元
公开(公告)号：US07707266B2
公开(公告)日：2010-04-27
申请号：US10997624
申请日：2004-11-23
申请人： Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Matthew Adiletta , Jeen-Xuan Miin , Bijoy Bose
发明人： Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Matthew Adiletta , Jeen-Xuan Miin , Bijoy Bose
IPC分类号： G06F13/00 , G06F15/173 , G06F15/16
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.
摘要翻译：用于多线程，多处理片上系统处理器单元的可扩展的高性能互连方案。实现该技术的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。在一个实施例中，机箱互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线路，用于目标的拉动数据总线写入和用于目标读取的推送数据总线。采用用于每个命令总线，拉数据总线和推数据总线的多路复用器电路来选择性地将给定集群连接到给定目标，以使命令和数据能够在给定集群和给定目标之间传递。

20. 发明申请

US20090132773A1 APPARATUS AND METHOD TO MERGE AND ALIGN DATA FROM DISTRIBUTED MEMORY CONTROLLERS 有权
标题翻译：从分布式存储器控制器中合并和对齐数据的装置和方法
公开(公告)号：US20090132773A1
公开(公告)日：2009-05-21
申请号：US12356284
申请日：2009-01-20
申请人： Rohit Natarajan , Sridhar Lakshmanamurthy , Chen-Chi Kuo
发明人： Rohit Natarajan , Sridhar Lakshmanamurthy , Chen-Chi Kuo
IPC分类号： G06F12/06
CPC分类号： G06F13/1684
摘要： We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory interface to manipulate data from at least two memory channels, each memory channel corresponding to a portion of a distributed memory, responsive to the predetermined memory access command. The memory interface includes a plurality of memory controllers coupled to the command bus, each memory controller being operable to control a corresponding memory channel responsive to the predetermined memory access command, and a push arbiter coupled to each memory controller. The push arbiter being is operable to merge and align data retrieved responsive to each split read align command.
摘要翻译：我们描述一种从分布式存储器控制器合并和对齐数据的系统和方法。存储器系统包括用于发送预定存储器访问命令的命令总线，以及存储器接口，用于响应于预定的存储器访问命令，操作来自至少两个存储器通道的数据，每个存储器通道对应于分布式存储器的一部分。存储器接口包括耦合到命令总线的多个存储器控制器，每个存储器控制器可操作以响应于预定存储器访问命令来控制相应的存储器通道，以及耦合到每个存储器控制器的推送仲裁器。推送仲裁器可操作以合并和对准根据每个拆分读取对准命令检索的数据。

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