专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06239467B1 Method of forming semiconductor devices using gate electrode length and spacer width for controlling drive current strength 有权
标题翻译：使用栅电极长度和间隔物宽度形成半导体器件以控制驱动电流强度的方法
公开(公告)号：US06239467B1
公开(公告)日：2001-05-29
申请号：US09183616
申请日：1998-10-30
申请人： Mark I. Gardner , H. Jim Fulford , Anthony Toprac
发明人： Mark I. Gardner , H. Jim Fulford , Anthony Toprac
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L22/20 , H01L29/6656 , H01L2924/0002 , Y10S257/90 , H01L2924/00
摘要： A semiconductor device having a controlled drive current strength is produced by varying spacer width to accommodate any variation in gate electrode length from a desired value. After formation of the gate electrode on a substrate, the length is measured and compared to a desired value. Based on any differences between the measured and desired values, the width of spacer is determined in order to counteract the variation in gate electrode length. This results in maintaining the desired channel length after dopant implanting, to provide the desired drive current strength. The present process permits close control over the drive current strength of semiconductor devices and also decreased variation within and between lots and corresponding increases in productivity.
摘要翻译：具有受控的驱动电流强度的半导体器件通过改变间隔物宽度来产生，以适应栅电极长度与期望值的任何变化。在基板上形成栅电极之后，测量长度并将其与期望值进行比较。基于测量值和期望值之间的任何差异，确定间隔物的宽度以抵消栅电极长度的变化。这导致在掺杂剂注入之后保持期望的沟道长度，以提供期望的驱动电流强度。本方法允许对半导体器件的驱动电流强度进行密切控制，并且还可以减少批次之间和批量之间的变化，并且相应地提高生产率。

12. 发明授权

US06225646B1 Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base 有权
标题翻译：集成电路结合存储单元和升高在绝缘基底上方的晶体管
公开(公告)号：US06225646B1
公开(公告)日：2001-05-01
申请号：US09483557
申请日：2000-01-14
申请人： Mark I. Gardner , H. Jim Fulford
发明人： Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L3300
CPC分类号： H01L27/0688 , H01L21/84 , H01L27/1203
摘要： An integrated circuit is presented. The integrated circuit may include a memory cell formed above an insulating base. The insulating base may either be arranged above a substrate or serve as a substrate itself. A transistor may be arranged above the memory cell. The transistor is preferably dielectrically isolated from the memory cell. In a preferred embodiment, a segmented substrate is arranged between the memory cell and transistor. The segmented substrate preferably includes a first conductive substrate layer arranged above and dielectrically spaced from the memory cell. A second conductive substrate layer may be formed above the first conductive substrate layer. The transistor may be arranged upon and within the second conductive substrate layer. Preferably, the segmented substrate further includes an intersubstrate dielectric layer interposed between the second conductive substrate layer and the first conductive substrate layer. The intersubstrate dielectric layer preferably serves to insulate the first conductive substrate layer from the second conductive substrate layer. An integrated circuit so configured may be fabricated with greater device density at reduced cost.
摘要翻译：介绍了一个集成电路。集成电路可以包括形成在绝缘基底上方的存储单元。绝缘基底可以布置在基底之上或用作基底本身。晶体管可以布置在存储器单元的上方。晶体管优选地与存储单元介电隔离。在优选实施例中，分段衬底被布置在存储器单元和晶体管之间。分段基板优选地包括布置在存储单元上方并与该存储单元间隔开的第一导电基板层。第二导电衬底层可以形成在第一导电衬底层的上方。晶体管可以布置在第二导电衬底层之上和之内。优选地，分段基板还包括插入在第二导电基板层和第一导电基板层之间的基板间电介质层。衬底间电介质层优选用于使第一导电衬底层与第二导电衬底层绝缘。如此构造的集成电路可以以更低的成本制造具有更大的器件密度。

13. 发明授权

US06225188B1 Self aligned method for differential oxidation rate at shallow trench isolation edge 有权
标题翻译：浅沟槽隔离边缘微分氧化率自对准方法
公开(公告)号：US06225188B1
公开(公告)日：2001-05-01
申请号：US09524447
申请日：2000-03-14
申请人： Derick J. Wristers , H. Jim Fulford , Mark I. Gardner
发明人： Derick J. Wristers , H. Jim Fulford , Mark I. Gardner
IPC分类号： H01L21265
CPC分类号： H01L21/76237
摘要： A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the portions relative proximal to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.
摘要翻译：提供其中在半导体衬底中形成至少一个隔离结构的半导体工艺。氧离子种类被引入半导体衬底的靠近隔离结构的部分，优选通过使用离子注入到倾斜或倾斜的衬底中。然后在半导体衬底的上表面上形成栅介质层。在半导体衬底的近端部分存在含氧物质增加了部分相对于离开隔离结构远端的部分氧化速率的氧化速率。以这种方式，在半导体衬底的近端部分上的栅极电介质的第一厚度大于半导体衬底的剩余部分上的栅极氧化物层的第二厚度。与隔离沟槽的不连续性相邻的增加的氧化物厚度减小了跨过氧化物的电场。

14. 发明授权

US06207520B1 Rapid thermal anneal with a gaseous dopant species for formation of lightly doped regions 失效
标题翻译：用气态掺杂剂物质快速热退火以形成轻掺杂区域
公开(公告)号：US06207520B1
公开(公告)日：2001-03-27
申请号：US08993918
申请日：1997-12-18
申请人： Mark I. Gardner , H. Jim Fulford
发明人： Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2251 , H01L21/2652 , H01L21/823807
摘要： Rapid thermal anneal with a gaseous dopant species for formation of a shallow lightly doped region is disclosed. In one embodiment of the invention, a method includes four steps. In the first step, at least one layer is applied over at least one gate over a semiconductor substrate. In the second step, an ion implantation is performed to form source and drain regions within the substrate. In the third step, the layers are removed. In the fourth step, a rapid thermal anneal with a gaseous dopant species is performed to form lightly doped regions within the substrate.
摘要翻译：公开了用于形成浅轻掺杂区域的气态掺杂物种的快速热退火。在本发明的一个实施例中，一种方法包括四个步骤。在第一步骤中，在半导体衬底上的至少一个栅极上施加至少一层。在第二步骤中，进行离子注入以在衬底内形成源区和漏区。在第三步中，层被去除。在第四步骤中，进行与气态掺杂剂物质的快速热退火以在衬底内形成轻掺杂区域。

15. 发明授权

US06169006A Semiconductor device having grown oxide spacers and method of manufacture thereof 失效
标题翻译：具有生长氧化物间隔物的半导体器件及其制造方法
公开(公告)号：US06169006A
公开(公告)日：2001-01-02
申请号：US09124604
申请日：1998-07-29
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L29/4983
摘要： A semiconductor device having grown oxide spacers and a method for manufacturing such a semiconductor device is provided. In one embodiment of the invention, a gate electrode is formed over a substrate, and an oxidation-resistant layer is formed adjacent to the gate electrode. The gate electrode is oxidized to grow an oxide layer on the gate electrode extending over the oxidation-resistant layer. One or more spacers then is formed adjacent to the gate electrode using the oxide layer.
摘要翻译：提供了具有生长的氧化物间隔物的半导体器件和制造这种半导体器件的方法。在本发明的一个实施例中，栅极电极形成在衬底上，并且与栅电极相邻形成抗氧化层。氧化栅极以在氧化层上延伸的栅电极上生长氧化物层。然后使用氧化物层在栅电极附近形成一个或多个间隔物。

16. 发明授权

US06168958A Semiconductor structure having multiple thicknesses of high-K gate dielectrics and process of manufacture therefor 有权
标题翻译：具有多个厚度的高K栅极电介质的半导体结构及其制造方法
公开(公告)号：US06168958A
公开(公告)日：2001-01-02
申请号：US09130494
申请日：1998-08-07
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L27/088 , H01L21/823462
摘要： A semiconductor structure having multiple thicknesses of high-k gate dielectrics and a process of manufacture. In one embodiment, semiconductor structure is provided that includes a substrate, and a high permittivity layer is disposed on the substrate, the high permittivity layer having two or more areas with different thicknesses. A plurality of gate electrodes are disposed in the two or more areas on the high permittivity layer. In another embodiment, a process for constructing a semiconductor structure includes depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness. A first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness. Selected portions of the high permittivity layer are then removed, whereby the high permittivity layer is reduced to a second thickness. Then a second set of gate electrodes are formed on the selected portions of the high permittivity layer having the second thickness.
摘要翻译：具有多个厚度的高k栅极电介质的半导体结构和制造工艺。在一个实施例中，提供了包括衬底的半导体结构，并且高介电常数层设置在衬底上，高电容率层具有两个或更多个具有不同厚度的区域。多个栅电极设置在高电容率层上的两个或更多个区域中。在另一个实施例中，用于构造半导体结构的工艺包括在衬底上沉积高介电常数层，高介电常数层具有第一厚度。在具有第一厚度的高电容率层上形成第一组一个或多个栅电极。然后去除高介电常数层的选定部分，由此将高介电常数层减小到第二厚度。然后，在具有第二厚度的高介电常数层的选定部分上形成第二组栅电极。

17. 发明授权

US6162687A Method of manufacturing semiconductor device having oxide-nitride gate insulating layer 失效
标题翻译：制造具有氧化物氮化物栅极绝缘层的半导体器件的方法
公开(公告)号：US6162687A
公开(公告)日：2000-12-19
申请号：US136464
申请日：1998-08-19
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L29/78 , H01L21/28 , H01L21/318 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： Generally, the present invention relates to semiconductor devices having an oxide-nitride gate insulating layer and methods of manufacture thereof. Consistent with the present invention a semiconductor device is formed by forming a nitrogen bearing oxide layer over a substrate and forming a nitride layer over the nitrogen bearing oxide layer. The thickness of the nitride layer is reduced and the nitride layer is annealed in an NH.sub.3 bearing ambient. The NH.sub.3 anneal may, for example, be performed before or after or while reducing the thickness of the nitride layer. One or more of the gate electrodes may then be formed over the nitride layer using the nitrogen bearing oxide layer and the nitride layer to insulate the gate electrode(s) from the substrate. This technique can, for example, provide a highly reliable and scaled gate insulating layer.
摘要翻译：通常，本发明涉及具有氧化物氮化物栅极绝缘层的半导体器件及其制造方法。根据本发明，通过在衬底上形成含氮氧化物层并在含氧氧化物层上形成氮化物层来形成半导体器件。氮化物层的厚度减小，并且氮化物层在NH 3承载环境中退火。 NH 3退火可以例如在减小氮化物层的厚度之前或之后进行。然后可以使用含氮的氧化物层和氮化物层在氮化物层上形成一个或多个栅电极，以使栅电极与衬底绝缘。该技术可以例如提供高可靠性和定标的栅极绝缘层。

18. 发明授权

US6140691A Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate 失效
标题翻译：具有从硅基底层隔离的低K介电材料的沟槽隔离结构
公开(公告)号：US6140691A
公开(公告)日：2000-10-31
申请号：US994701
申请日：1997-12-19
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/762 , H01L29/00 , H01L23/58 , H01L29/76 , H01L29/94
CPC分类号： H01L21/76224
摘要： A trench isolation structure is provided which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. As a result, the lateral width of the isolation structure may be decreased without significantly increasing the capacitance between those active areas. In an embodiment, a fabrication process for the trench isolation structure may include a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner is thermally grown upon the sidewalls and base of the trench. A layer of low K dielectric material is deposited across the oxide liner. A fill oxide is then formed upon the layer of dielectric material. The resulting trench isolation structure includes a low K dielectric material interposed between an oxide liner and a fill oxide. The trench isolation structure is less likely to experience current leakage during the operation of an ensuing integrated circuit employing the isolation structure.
摘要翻译：提供了一种沟槽隔离结构，其包括具有相对较低的介电常数K的介电材料，K大约小于3.8。由沟槽隔离结构隔开的与K成正比的有源区之间的电容因此减小。结果，可以减小隔离结构的横向宽度，而不显着增加这些有源区域之间的电容。在一个实施例中，用于沟槽隔离结构的制造工艺可以包括在形成有掩模层的半导体衬底内蚀刻沟槽。在沟槽的侧壁和基底上热生长氧化物衬垫。一层低K电介质材料沉积在氧化物衬垫两侧。然后在电介质材料层上形成填充氧化物。所形成的沟槽隔离结构包括介于氧化物衬垫和填充氧化物之间的低K电介质材料。在采用隔离结构的随后的集成电路的操作期间，沟槽隔离结构不太可能经历电流泄漏。

19. 发明授权

US6124188A Semiconductor device and fabrication method using a germanium sacrificial gate electrode plug 有权
标题翻译：使用锗牺牲栅电极插头的半导体器件和制造方法
公开(公告)号：US6124188A
公开(公告)日：2000-09-26
申请号：US203012
申请日：1998-12-01
申请人： Mark I. Gardner , H. Jim Fulford
发明人： Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L21/336 , H01L21/60 , H01L29/417 , H01L21/3205
CPC分类号： H01L21/76897 , H01L29/41775 , H01L29/41783 , H01L29/66575 , H01L29/66545
摘要： Semiconductor devices and fabrication processes which rely on the use of sacrificial gate electrode plugs are provided. In one embodiment, a germanium bearing plug is used to form a gate electrode. The germanium plug may advantageously be removed using a solution which leaves underlying portions of the oxide layer intact. In another embodiment, spacers are formed adjacent sidewalls of a sacrificial plug and active regions are formed adjacent the sacrificial plug. The sacrificial plug is then removed to form an opening between the spacers and a conductive layer is deposited over the substrate to form a gate electrode and active region contacts.
摘要翻译：提供依赖于使用牺牲栅电极插头的半导体器件和制造工艺。在一个实施例中，使用锗轴承塞形成栅电极。有利地可以使用将氧化物层的下面部分完整留下的溶液除去锗塞。在另一个实施例中，间隔物形成在牺牲塞的侧壁附近，有源区邻近牺牲插塞形成。然后去除牺牲塞以在间隔件之间形成开口，并且在衬底上沉积导电层以形成栅电极和有源区接触。

20. 发明授权

US6107130A CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions 有权
标题翻译： CMOS集成电路具有用于产生与PMOS源极/漏极结不相似的分级NMOS源极/漏极结的牺牲金属间隔物
公开(公告)号：US6107130A
公开(公告)日：2000-08-22
申请号：US189235
申请日：1998-11-10
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/823814 , Y10S257/90
摘要： An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.
摘要翻译：形成集成电路，其中NMOS晶体管的结形成为不同于PMOS晶体管的结。 NMOS晶体管包括LDD区域，MDD区域和重的浓度源极/漏极区域。相反，PMOS晶体管包括LDD区域和源极/漏极区域。 NMOS晶体管结形成为不同于PMOS晶体管结，以考虑到相掺杂剂相对于PMOS掺杂剂的移动性较小。因此，LDD面积的减小和包含MDD面积在NMOS器件中提供更低的源极/漏极电阻和更高的欧姆连接性。 PMOS结包括相对较大的LDD面积，以便将高度移动的，高浓度的硼原子从PMOS沟道拉出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式