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11. 发明申请

US20110111586A1 Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device 审中-公开
标题翻译：设置完全硅化半导体器件的功能的方法及相关器件
公开(公告)号：US20110111586A1
公开(公告)日：2011-05-12
申请号：US13004162
申请日：2011-01-11
申请人： Luigi Colombo , Mark R. Visokay , James J. Chambers
发明人： Luigi Colombo , Mark R. Visokay , James J. Chambers
IPC分类号： H01L21/3205
CPC分类号： H01L21/823835 , H01L21/28079 , H01L21/28097 , H01L21/28176 , H01L21/28518 , H01L21/76819 , H01L21/823842
摘要： A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.
摘要翻译：一种设置完全硅化半导体器件的功能的方法及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物上的多晶硅层层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 电介质层界面。

12. 发明授权

US07601578B2 Defect control in gate dielectrics 有权
标题翻译：栅极电介质缺陷控制
公开(公告)号：US07601578B2
公开(公告)日：2009-10-13
申请号：US11924132
申请日：2007-10-25
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Antonio Luis Pacheco Rotondaro
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Antonio Luis Pacheco Rotondaro
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译：一种改善高卡门电介质膜（104）性能的方法。对高卡帕膜（104）进行两步退火处理。第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。

13. 发明授权

US07229873B2 Process for manufacturing dual work function metal gates in a microelectronics device 有权
标题翻译：在微电子器件中制造双功能金属栅极的工艺
公开(公告)号：US07229873B2
公开(公告)日：2007-06-12
申请号：US11200741
申请日：2005-08-10
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/04 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842 , H01L29/66545
摘要： The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.
摘要翻译：本发明提供一种形成双功函数金属栅极微电子器件200的方法。在一个方面，该方法包括形成nMOS和pMOS堆叠栅极结构315a和315b。 nMOS和pMOS堆叠栅极结构315a和315b各自包括栅极电介质205，位于栅极电介质205上方的第一金属层305和位于第一金属层305上方的牺牲栅极层310。该方法还包括在nMOS或pMOS堆叠栅极结构中的至少一个中去除牺牲栅极层310，从而形成栅极开口825并修改栅极开口825内的第一金属层305以形成具有所需工作的栅电极功能。

14. 发明授权

US07067434B2 Hydrogen free integration of high-k gate dielectrics 有权
标题翻译：高k栅极电介质的无氢结合
公开(公告)号：US07067434B2
公开(公告)日：2006-06-27
申请号：US10745449
申请日：2003-12-22
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L21/302
CPC分类号： H01L21/28194 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31111 , H01L21/3144 , H01L21/3145 , H01L21/31608 , H01L21/3185 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , Y10S438/91 , Y10S438/954
摘要： The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.
摘要翻译：本发明涉及在不存在氢的情况下形成晶体管，或者在显着减少量的氢的存在下。以这种方式，可以利用高k材料在晶体管中形成栅极电介质层，并且便于器件缩放，同时减轻可通过存在氢和/或含氢化合物引入高k材料的缺陷。

15. 发明授权

US08575014B2 Semiconductor device fabricated using a metal microstructure control process 有权
标题翻译：使用金属微结构控制工艺制造的半导体器件
公开(公告)号：US08575014B2
公开(公告)日：2013-11-05
申请号：US13404840
申请日：2012-02-24
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L21/22
CPC分类号： H01L21/28079 , H01L21/02068 , H01L21/3003 , H01L21/321 , H01L21/823842
摘要： The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
摘要翻译：本发明提供了一种制造半导体器件的方法，该方法包括将金属栅极层放置在栅极电介质层上，其中金属栅极层具有晶体取向，并通过对金属栅极层进行金属栅极层的重新取向来取向晶体取向进行氢退火。

16. 发明申请

US20100187613A1 Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device 审中-公开
标题翻译：设置完全硅化半导体器件的功能的方法及相关器件
公开(公告)号：US20100187613A1
公开(公告)日：2010-07-29
申请号：US12750916
申请日：2010-03-31
申请人： Luigi Colombo , Mark R. Visokay , James J. Chambers
发明人： Luigi Colombo , Mark R. Visokay , James J. Chambers
IPC分类号： H01L27/092
CPC分类号： H01L21/823835 , H01L21/28079 , H01L21/28097 , H01L21/28176 , H01L21/28518 , H01L21/76819 , H01L21/823842
摘要： A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.
摘要翻译：一种设置完全硅化半导体器件的功能的方法及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物上的多晶硅层层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 电介质层界面。

17. 发明申请

US20070278584A1 SEMICONDUCTOR DEVICE FABRICATED USING A METAL MICROSTRUCTURE CONTROL PROCESS 有权
标题翻译：使用金属微结构控制过程制造的半导体器件
公开(公告)号：US20070278584A1
公开(公告)日：2007-12-06
申请号：US11421671
申请日：2006-06-01
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L29/94
CPC分类号： H01L21/28079 , H01L21/02068 , H01L21/3003 , H01L21/321 , H01L21/823842
摘要： The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
摘要翻译：本发明提供了一种制造半导体器件的方法，该方法包括将金属栅极层放置在栅极电介质层上，其中金属栅极层具有晶体取向，并通过对金属栅极层进行金属栅极层的重新取向来取向晶体取向进行氢退火。

18. 发明授权

US06852645B2 High temperature interface layer growth for high-k gate dielectric 有权
标题翻译：高k栅极电介质的高温界面层生长
公开(公告)号：US06852645B2
公开(公告)日：2005-02-08
申请号：US10367429
申请日：2003-02-13
申请人： Luigi Colombo , James J. Chambers , Antonio L. P. Rotondaro , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Antonio L. P. Rotondaro , Mark R. Visokay
IPC分类号： C23C28/00 , H01L21/02 , H01L21/28 , H01L21/316 , H01L29/51 , H01L29/78 , H01L21/469
CPC分类号： H01L21/28185 , C23C28/00 , H01L21/02238 , H01L21/02255 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/31155 , H01L21/31662 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention pertains to methods for forming high quality thin interface oxide layers suitable for use with high-k gate dielectrics in the manufacture of semiconductor devices. An ambient that contains oxygen and a reducing agent is utilized to grow the layers. The oxygen facilitates growth of the layers, while the reducing agent simultaneously counteracts that growth. The rate of growth of the layers can thus be controlled by regulating the partial pressure of the reducing agent, which is the fraction of the reducing agent in the gas phase times the total pressure. Controlling and slowing the growth rate of the layers facilitates production of the layers to thicknesses of about 10 Angstroms or less at temperatures of about 850 degrees Celsius or more. Growing the layers at high temperatures facilitates better bonding and production of higher quality layers, which in turn yields better performing and more reliable resulting products.
摘要翻译：本发明涉及在制造半导体器件时形成适用于高k栅极电介质的高品质薄界面氧化物层的方法。使用含有氧和还原剂的环境来生长层。氧促进层的生长，而还原剂同时抵消该生长。因此，可以通过调节还原剂的分压来控制层的生长速度，还原剂的分压是气相中还原剂的分数乘以总压力。控制和减缓层的生长速率有助于在约850摄氏度或更高的温度下将层的生产达到约10埃或更小的厚度。在高温下生长层有助于更好地粘合和生产更高质量的层，这又产生更好的性能和更可靠的结果产品。

19. 发明授权

US07625807B2 Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication 有权
标题翻译：用于减轻浅沟槽隔离制造的蚀刻停止限幅的方法和系统
公开(公告)号：US07625807B2
公开(公告)日：2009-12-01
申请号：US11678107
申请日：2007-02-23
申请人： Manuel A. Quevedo-Lopez , James J. Chambers , Leif Christian Olsen
发明人： Manuel A. Quevedo-Lopez , James J. Chambers , Leif Christian Olsen
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/823807 , H01L21/823878
摘要： The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.
摘要翻译：本发明通过在沟槽填充操作期间保持蚀刻停止层（206）的形状和密度来促进半导体制造。通过在沟槽填充操作之前在蚀刻停止层（206）上形成保护合金衬垫层（310）来保持蚀刻停止层（206）的形状和密度。保护合金衬套（310）由对沟槽填充操作中使用的材料具有耐受性的合金构成。结果，减轻了对蚀刻停止层（206）的削波和/或损伤，从而有利于采用蚀刻停止层（206）的随后的平坦化工艺。此外，形成的保护合金（310）的厚度和组成（1706）的选择产生施加到未成形晶体管器件的沟道区域的应力量和类型（1704），最终提供了沟道迁移率的改善。

20. 发明授权

US07119386B2 Versatile system for triple-gated transistors with engineered corners 有权
标题翻译：具有工程角的三栅晶体管的多功能系统
公开(公告)号：US07119386B2
公开(公告)日：2006-10-10
申请号：US11221103
申请日：2005-09-07
申请人： Mark R. Visokay , James J. Chambers
发明人： Mark R. Visokay , James J. Chambers
IPC分类号： H01L29/76
CPC分类号： H01L29/7831 , H01L29/66484
摘要： The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.
摘要翻译：本发明提供一种利用标准半导体衬底（302）制造三栅晶体管段（300）的系统。衬底具有沿着其上表面以远侧分开的关系形成的多个隔离区域（304），其限定沟道区域（306）。形式结构（308）设置在隔离区顶部，并且限定通道区域上的通道体区域（310）。通道体结构（316）设置在通道主体区域内，并被设计成沿着其上暴露表面的周边提供钝角或边缘（318）。然后去除形式结构，并执行后续处理。

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