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    • 11. 发明授权
    • Pulse train writing of worm storage device
    • 脉冲串写蜗杆存储装置
    • US06434048B1
    • 2002-08-13
    • US09908901
    • 2001-07-20
    • Lung T. TranManish Sharma
    • Lung T. TranManish Sharma
    • G11C700
    • G11C7/1084G11C7/1006G11C7/1078
    • A method and circuit write a memory cell. The method applies a pulse train to a write line connected to the memory cell. The number of pulses in the pulse train is not predetermined. The method compares a value on the input side of the cell to a reference value, wherein the input side of the memory cell provides an indication that a writing operation is complete. The method discontinues the pulse train on the write line, in response to the comparing step, preferably if the value on the write line exceeds the reference value. Preferably, the pulses are short in width and large in magnitude. The method may optionally count the number of pulses in the pulse train, and discontinue the pulse train on the write line and/or declare the cell as unusable if the number of pulses exceeds a predetermined maximum. The circuit comprises a pulse train generator and a comparator. The pulse train generator has an output and an enable input. The output is connected to a write line connected to the memory cell. The output, when enabled, carries a pulse train. The comparator has two inputs and an output. One of the inputs is connected to the write line. The other of the inputs is connected to a reference. The output is connected to the enable input of the pulse train generator, whereby the pulse train generator is disabled or enabled depending upon the comparator output. Optionally, the circuit further comprises a counter that counts pulses and disables the pulse train generator after a predetermined maximum number of pulses. A complete memory system comprises an array of memory cells, a write line, and a pulse train generator and comparator as described above.
    • 一种方法和电路写入一个存储单元。 该方法将脉冲串应用于连接到存储单元的写入线。 脉冲串中的脉冲数不是预定的。 该方法将小区的输入侧的值与参考值进行比较,其中存储单元的输入侧提供写入操作完成的指示。 该方法响应于比较步骤中止写入线上的脉冲序列,优选地,如果写入线上的值超过参考值。 优选地,脉冲的宽度较短,而且幅度较大。 该方法可以可选地计数脉冲串中的脉冲数,并且如果脉冲数超过预定最大值,则在写入线上中止脉冲序列和/或将单元声明为不可用。 电路包括脉冲串发生器和比较器。 脉冲串发生器具有输出和使能输入。 输出连接到连接到存储单元的写入线。 输出,当使能时,携带脉冲串。 比较器有两个输入和一个输出。 其中一个输入连接到写入线。 另一个输入连接到引用。 输出连接到脉冲串发生器的使能输入端,根据比较器输出,脉冲串发生器被禁止或使能。 可选地,电路还包括计数器,其计数脉冲并且在预定的最大脉冲数之后禁用脉冲序列发生器。 完整的存储器系统包括如上所述的存储器单元阵列,写入线以及脉冲序列发生器和比较器。
    • 12. 发明授权
    • Read operations on multi-bit memory cells in resistive cross point arrays
    • 读取电阻式交叉点阵列中多位存储单元的操作
    • US06754097B2
    • 2004-06-22
    • US10234511
    • 2002-09-03
    • Manish SharmaLung T. Tran
    • Manish SharmaLung T. Tran
    • G11C1100
    • G11C11/56G11C11/1673G11C11/5607G11C11/5678G11C13/0004G11C13/004G11C2013/005
    • A data storage device includes a resistive cross point array of memory cells. Each memory cell includes serially-connected first and second resistive devices. Each resistive device has programmable first and second resistance states. The data storage device further includes pluralities of first, second and third conductors, and a read circuit. Each first conductor is connected to data layers of a column of the first magnetoresistive devices; each second conductor is connected to data layers of a column of second magnetoresistive devices; and each third conductor is between reference layers of a row of first and second magnetoresistive devices. The read circuit applies different first and second voltages during read operations. The first voltage is applied to the first and second conductors crossing a selected memory cell; and the second voltage is applied to the third conductor crossing the selected memory cell.
    • 数据存储装置包括存储单元的电阻交叉点阵列。 每个存储单元包括串联连接的第一和第二电阻器件。 每个电阻器件具有可编程的第一和第二电阻状态。 数据存储装置还包括多个第一,第二和第三导体和读取电路。 每个第一导体连接到第一磁阻器件的列的数据层; 每个第二导体连接到第二磁阻器件列的数据层; 并且每个第三导体位于一列第一和第二磁阻器件的参考层之间。 读取电路在读取操作期间施加不同的第一和第二电压。 第一电压被施加到与所选择的存储单元交叉的第一和第二导体; 并且第二电压被施加到与选择的存储单元交叉的第三导体。
    • 17. 发明授权
    • Crossover operation in A 1+1 protection switching environment
    • A 1 + 1保护切换环境中的交叉运行
    • US08824273B2
    • 2014-09-02
    • US13027610
    • 2011-02-15
    • Manish SharmaXinkuan ZhouJoe PollandJun-Ming Wu
    • Manish SharmaXinkuan ZhouJoe PollandJun-Ming Wu
    • H04L1/00H04L29/14H04L12/56H04L12/28H04L12/26H04M11/06H04L12/24
    • H04L69/40H04L12/2856H04L12/2898H04L41/0654H04L41/0681H04L41/0686H04L43/0811H04L45/28H04M11/062
    • A communication system that comprises at least two links to carry signals, a first communication unit and a second communication unit. The first communication unit comprises at least two ports, each port configured to transmit and receive signals; and a logic unit configured to process the signals transmitted and received by each of the at least two ports in the first communication unit. The second communication unit comprises at least two ports, each port configured to transmit and receive signals and coupled to a respective one of the at least two ports in the first communication unit via a respective one of the at least two links; a programmable logic unit configured to process the signals transmitted and received by each of the at least two ports in the second communication unit; and a processor. The processor is configured to detect a crossover connection between one of the at least two ports in the second communication unit and the respective one of the at least two ports in the first communication unit based on an analysis of a pair identifier field in a message received at the second communication unit, wherein the pair identifier field is separate from the address field of the received message.
    • 一种包括至少两个用于承载信号的链路的通信系统,第一通信单元和第二通信单元。 第一通信单元包括至少两个端口,每个端口被配置为发送和接收信号; 以及逻辑单元,被配置为处理由所述第一通信单元中的所述至少两个端口中的每一个发送和接收的信号。 所述第二通信单元包括至少两个端口,每个端口被配置为经由所述至少两个链路中的相应一个发送和接收信号并且耦合到所述第一通信单元中的所述至少两个端口中的相应一个端口; 可编程逻辑单元,被配置为处理由所述第二通信单元中的所述至少两个端口中的每一个发送和接收的信号; 和处理器。 处理器被配置为基于对所接收的消息中的对标识符字段的分析来检测第二通信单元中的至少两个端口中的一个端口与第一通信单元中的至少两个端口中的相应一个之间的交叉连接 在第二通信单元处,其中对标识符字段与接收到的消息的地址字段分离。
    • 20. 发明申请
    • M-PAIR MODE PROTECTION SWITCHING
    • M-PAIR模式保护开关
    • US20130021899A1
    • 2013-01-24
    • US13187306
    • 2011-07-20
    • Joe PollandClifton PowersManish SharmaLaxman R. AnneYiu Lam Chan
    • Joe PollandClifton PowersManish SharmaLaxman R. AnneYiu Lam Chan
    • H04L12/26
    • H04L12/2898H04M11/062
    • A communication comprises a plurality of digital subscriber line (DSL) links, a first node having at least one application port configured for an elastic service and a plurality of DSL ports, and a second node having at least one application port configured for an elastic service and a plurality of DSL ports. Each of the first and second nodes is configured to interleave data received over the at least one application port across the plurality of DSL ports, each DSL port allocated a set of DSL timeslots for transport of the data received over the at least one application port. When a failure is detected on one of the DSL links, each of the first and second nodes is configured to interleave the data received over the at least one application port across the remaining DSL ports not connected to the failed DSL link without adjusting the set of DSL timeslots allocated to each of the remaining DSL ports for transport of the data from the at least one application port.
    • 通信包括多个数字用户线(DSL)链路,具有配置用于弹性服务的至少一个应用端口和多个DSL端口的第一节点以及具有被配置用于弹性服务的至少一个应用端口的第二节点 和多个DSL端口。 第一和第二节点中的每一个被配置为交织跨多个DSL端口上的至少一个应用端口接收的数据,每个DSL端口分配一组DSL时隙,用于传输在至少一个应用端口上接收的数据。 当在DSL链路之一上检测到故障时,第一和第二节点中的每一个被配置成交错在不连接到故障DSL链路的剩余DSL端口上的至少一个应用端口上接收的数据,而不调整该组 分配给每个剩余DSL端口的DSL时隙用于从至少一个应用端口传输数据。