专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08171377B2 System to improve memory reliability and associated methods 有权
标题翻译：系统提高内存可靠性和相关方法
公开(公告)号：US08171377B2
公开(公告)日：2012-05-01
申请号：US12023374
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1044 , H03M13/1515
摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
摘要翻译：一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。

12. 发明授权

US08185800B2 System for error control coding for memories of different types and associated methods 有权
标题翻译：用于不同类型和相关方法的存储器的错误控制编码系统
公开(公告)号：US08185800B2
公开(公告)日：2012-05-22
申请号：US12023408
申请日：2008-01-31
申请人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
发明人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/35 , H03M13/353 , H03M13/3707 , H03M13/6511 , H03M13/6516
摘要： A system to improve error control coding. An example system includes memory chips of at least two different kinds. The system also includes error control encoder circuitry to substantially encode data for storage in any memory rank. The system further includes error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.
摘要翻译：一种改进错误控制编码的系统。示例系统包括至少两种不同类型的存储器芯片。该系统还包括错误控制编码器电路，用于基本上编码数据以存储在任何存储器级中。该系统还包括错误控制解码器电路，以基本上解码从任何存储器等级接收的编码数据。错误解码器电路由慢解码器和快速解码器组成。

13. 发明申请

US20100287454A1 System to Improve Error Code Decoding Using Historical Information and Associated Methods 有权
标题翻译：使用历史信息和相关方法改进错误代码解码的系统
公开(公告)号：US20100287454A1
公开(公告)日：2010-11-11
申请号：US12023445
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve error code decoding using historical information may include storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system may also generate a memory rank score for each memory rank. The system may also include an error control decoder that may use the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.
摘要翻译：使用历史信息改进错误代码解码的系统可以包括分割成存储器排名的存储器，以及记录具有每个存储器级别故障的符号的表。系统还可以为每个存储器等级产生存储器等级分数。系统还可以包括错误控制解码器，其可以在访问每个存储器级时使用存储器等级分数，以便确定是否应该纠正错误。

14. 发明授权

US08615689B2 Correcting errors in longitudinal position (LPOS) words 有权
标题翻译：校正纵向位置误差（LPOS）词
公开(公告)号：US08615689B2
公开(公告)日：2013-12-24
申请号：US13612396
申请日：2012-09-12
申请人： William J. Kabelac , Barry M. Trager , Shmuel Winograd
发明人： William J. Kabelac , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： G11B27/107 , G11B27/24 , G11B27/36 , G11B2220/93
摘要： A method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes first encoding positional information onto the tape within the 36-bit LPOS words using each LPOS word's 8-bit sync mark field, and six of each LPOS word's 4-bit symbol fields, wherein 6 of 24 total bits comprise the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields are utilized as parity bits. The magnetic tape storage system passes the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information and detecting and correcting both ambiguous bits and single erroneous bit errors.
摘要翻译：一种用于在线性磁带打开（LTO）磁存储磁带上存储数据的磁带存储系统中的纵向位置（LPOS）检测方法，该数据包括具有纠错能力的奇数和偶数36位LPOS字。该方法包括使用每个LPOS字的8位同步标记字段以及每个LPOS字的4位符号字段中的六个，在36位LPOS字中的位置信息之上编码位置信息，其中24个总比特中的6个包括编码的8 位同步标记字段：Sy和六个4位符号字段用作奇偶校验位。磁带存储系统以已知速度将穿过伺服读取器/写入器的具有纠错能力的奇数和偶数LPOS字编码的LTO磁存储带纵向跨越伺服读取器/写入器，对编码的位置信息进行解码，并检测和校正两个不明确的位和单个错误位错误。

15. 发明申请

US20130198705A1 CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US20130198705A1
公开(公告)日：2013-08-01
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

16. 发明授权

US08640065B2 Circuit verification using computational algebraic geometry 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US08640065B2
公开(公告)日：2014-01-28
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

17. 发明申请

US20120005561A1 REDUCED CIRCUIT IMPLEMENTATION OF ENCODER AND SYNDROME GENERATOR 有权
标题翻译：编码器和综合发生器的减少电路实现
公开(公告)号：US20120005561A1
公开(公告)日：2012-01-05
申请号：US13168559
申请日：2011-06-24
申请人： Barry M. Trager , Shmuel Winograd
发明人： Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1515 , H03M13/1595
摘要： An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(28) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.
摘要翻译：错误校正方法和系统包括编码器和综合发生器，其并行操作以减少用于计算用于纠错码的校验符号和校正子的电路的数量。系统和方法一次计算对一致性的贡献和一次检查符号，而不是1个符号。因此，偶数综合征可以计算为奇数综合征的功率。此外，系统分配符号地址，使得对于具有72个符号的示例GF（28），具有不同于单位的立方根的三（3）个地址块，以允许数据符号被组合以减小大小和奇异综合征电路的复杂性。此外，用于产生检查符号的实现电路是使用校正位置的校正子矩阵的部分的倒数从校正子电路导出的。

18. 发明申请

US20130003213A1 CORRECTING ERRORS IN LONGITUDINAL POSITION (LPOS) WORDS 有权
标题翻译：纠正长期位置错误（LPOS）
公开(公告)号：US20130003213A1
公开(公告)日：2013-01-03
申请号：US13612396
申请日：2012-09-12
申请人： William J. Kabelac , Barry M. Trager , Shmuel Winograd
发明人： William J. Kabelac , Barry M. Trager , Shmuel Winograd
IPC分类号： G11B5/09 , G11B5/008
CPC分类号： G11B27/107 , G11B27/24 , G11B27/36 , G11B2220/93
摘要： A method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes first encoding positional information onto the tape within the 36-bit LPOS words using each LPOS word's 8-bit sync mark field, and six of each LPOS word's 4-bit symbol fields, wherein 6 of 24 total bits comprise the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields are utilized as parity bits. The magnetic tape storage system passes the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information and detecting and correcting both ambiguous bits and single erroneous bit errors.
摘要翻译：一种用于在线性磁带打开（LTO）磁存储磁带上存储数据的磁带存储系统中的纵向位置（LPOS）检测方法，该数据包括具有纠错能力的奇数和偶数36位LPOS字。该方法包括使用每个LPOS字的8位同步标记字段以及每个LPOS字的4位符号字段中的六个，在36位LPOS字中的位置信息之上编码位置信息，其中24个总比特中的6个包括编码的8 位同步标记字段：Sy和六个4位符号字段用作奇偶校验位。磁带存储系统以已知速度将穿过伺服读取器/写入器的具有纠错能力的奇数和偶数LPOS字编码的LTO磁存储带纵向跨越伺服读取器/写入器，对编码的位置信息进行解码，并检测和校正两个不明确的位和单个错误位错误。

19. 发明授权

US08271857B2 Correcting errors in longitudinal position (LPOS) words 有权
标题翻译：校正纵向位置误差（LPOS）词
公开(公告)号：US08271857B2
公开(公告)日：2012-09-18
申请号：US12119975
申请日：2008-05-13
申请人： William J. Kabelac , Barry M. Trager , Shmuel Winograd
发明人： William J. Kabelac , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： G11B27/107 , G11B27/24 , G11B27/36 , G11B2220/93
摘要： The invention includes a method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes steps of encoding positional information onto the magnetic storage tape within the odd and even 36-bit LPOS words using each LPOS word's 8-bit sync mark field, Sy, and six of each LPOS word's 4-bit symbol fields, L0, L1, L2 L3, L4, and L5, wherein 6 of 24 total bits comprising the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields: L0, L1, L2 L3, L4, and L5 are utilized as parity bits, operating the magnetic tape storage system by passing the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information by reading either two words sequentially or two words simultaneously, the simultaneous reading requiring that the LPOS words include servo band numbers and detecting and correcting both ambiguous bits and single erroneous bit errors.
摘要翻译：本发明包括一种用于在线性磁带打开（LTO）磁存储磁带上存储数据的磁带存储系统中的纵向位置（LPOS）检测方法，该数据包括具有纠错能力的奇数和偶数的36位LPOS字。该方法包括使用每个LPOS字的8位同步标记字段Sy和每个LPOS字的4位符号字段L0中的6个将位置信息编码到奇数和偶数36位LPOS字中的位置信息的步骤， L1，L2 L3，L4和L5，其中包括编码的8位同步标记字段Sy的24个总比特中的6个和6个4位符号字段：L0，L1，L2 L3，L4和L5用作奇偶校验位，通过以已知速度通过伺服读取器/写入器将具有纠错能力的奇数和偶数LPOS字编码的LTO磁存储带纵向跨越伺服读取器/写入器来操作磁带存储系统，通过读取两个字来解码编码的位置信息同时读取，要求LPOS字包括伺服频带号，并且检测和校正两个不明确的位和单个错误位错误。

20. 发明授权

US08010875B2 Error correcting code with chip kill capability and power saving enhancement 有权
标题翻译：错误纠正代码具有芯片杀死能力和节能增强
公开(公告)号：US08010875B2
公开(公告)日：2011-08-30
申请号：US11768559
申请日：2007-06-26
申请人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
发明人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
摘要翻译：公开了一种用于检测计算机存储器系统中的存储器芯片故障的方法和系统。该方法包括以下步骤：从一组用户数据芯片访问用户数据，以及使用来自一组系统数据芯片的数据来测试用户数据的错误。该测试通过从用户数据生成检查符号序列来完成，将用户数据分组成数据符号序列，并计算指定的综合征序列。如果所有的综合征为零，则用户数据没有错误。如果其中一个校正子不为零，则计算一组鉴别符表达式，并用于确定是否发生单个或双重符号错误。在优选实施例中，使用少于两个全系统数据芯片来测试和校正用户数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式