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11. 发明申请

US20060226547A1 SEMICONDUCTOR CHIP CAPABLE OF IMPLEMENTING WIRE BONDING OVER ACTIVE CIRCUITS 有权
标题翻译：在有源电路上实现线路连接的半导体芯片
公开(公告)号：US20060226547A1
公开(公告)日：2006-10-12
申请号：US11422330
申请日：2006-06-06
申请人： Kun-Chih Wang , Bing-Chang Wu
发明人： Kun-Chih Wang , Bing-Chang Wu
IPC分类号： H01L23/52
CPC分类号： H01L24/05 , H01L23/53238 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , Y10T428/24917 , Y10T428/265 , H01L2924/00014
摘要： A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.
摘要翻译：强化焊盘结构包括限定在应力缓冲电介质层上的可粘合金属层和在应力缓冲介质层下设置的第一金属间电介质（IMD）层中的中间金属层。中间金属层位于可接合的金属层的正下方，并且与可结合金属层电连接，多个通孔与可结合的金属层集成。在第一IMD层下面的第二IMD层中金属框架被镶嵌。金属框架直接位于中间金属层的正下方，用于抵抗在接合期间施加在可接合金属层上的机械应力，当所述应力缓冲介电层的厚度大于2000埃时，可以省略镶嵌的金属框架。包括集成电路的有源电路部件的有源电路部分位于金属框架的正下方。

12. 发明申请

US20060186545A1 SEMICONDUCTOR CHIP CAPABLE OF IMPLEMENTING WIRE BONDING OVER ACTIVE CIRCUITS 有权
标题翻译：在有源电路上实现线路连接的半导体芯片
公开(公告)号：US20060186545A1
公开(公告)日：2006-08-24
申请号：US11379572
申请日：2006-04-21
申请人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
发明人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/53228 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.
摘要翻译：提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘与顶部互连金属层之间的第一通孔塞。半导体芯片还至少包括互连金属层，在互连金属层和焊盘结构之间的至少第二通孔插塞以及位于半导体衬底上的焊盘结构下方的有源电路。

13. 发明申请

US20050202221A1 SEMICONDUCTOR CHIP CAPABLE OF IMPLEMENTING WIRE BONDING OVER ACTIVE CIRCUITS 有权
标题翻译：在有源电路上实现线路连接的半导体芯片
公开(公告)号：US20050202221A1
公开(公告)日：2005-09-15
申请号：US10907959
申请日：2005-04-22
申请人： Kun-Chih Wang , Bing-Chang Wu
发明人： Kun-Chih Wang , Bing-Chang Wu
IPC分类号： H01L23/485 , B32B3/00
CPC分类号： H01L24/05 , H01L23/53238 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , Y10T428/24917 , Y10T428/265 , H01L2924/00014
摘要： A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.
摘要翻译：强化焊盘结构包括限定在应力缓冲电介质层上的可粘合金属层和在应力缓冲介质层下设置的第一金属间电介质（IMD）层中的中间金属层。中间金属层位于可接合的金属层的正下方，并且与可结合金属层电连接，多个通孔与可结合的金属层集成。在第一IMD层下面的第二IMD层中金属框架被镶嵌。金属框架直接位于中间金属层的正下方，用于抵抗在接合期间施加在可接合金属层上的机械应力，当所述应力缓冲介电层的厚度大于2000埃时，可以省略镶嵌的金属框架。包括集成电路的有源电路部件的有源电路部分位于金属框架的正下方。

14. 发明授权

US06348398B1 Method of forming pad openings and fuse openings 失效
标题翻译：形成垫片开口和保险丝孔的方法
公开(公告)号：US06348398B1
公开(公告)日：2002-02-19
申请号：US09849131
申请日：2001-05-04
申请人： Kun-Chih Wang
发明人： Kun-Chih Wang
IPC分类号： H01L2182
CPC分类号： H01L24/03 , H01L21/76802 , H01L23/5256 , H01L24/02 , H01L24/05 , H01L2224/02166 , H01L2224/05599 , H01L2224/05624 , H01L2224/05647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/00014
摘要： A method of forming pad openings and fuse openings over a wafer. A wafer having pads and fuses thereon is provided. A passivation layer and a photoresist layer are sequentially formed over the wafer. A photo-exposure and development operation is conducted to remove the photoresist layer above the pads. An etching operation is conducted to remove the passivation layer above the pads as well as the photoresist layer and a portion of the passivation layer above the fuses. Finally, the photoresist layer is removed.
摘要翻译：在晶片上形成焊盘开口和熔断器开口的方法。提供其上具有焊盘和保险丝的晶片。在晶片上依次形成钝化层和光致抗蚀剂层。进行曝光和显影操作以去除衬垫上方的光致抗蚀剂层。进行蚀刻操作以去除焊盘上方的钝化层以及保护层上方的光致抗蚀剂层和钝化层的一部分。最后，去除光致抗蚀剂层。

15. 发明授权

US06080646A Method of fabricating a metal-oxide-semiconductor transistor with a metal gate 失效
标题翻译：用金属栅极制造金属氧化物半导体晶体管的方法
公开(公告)号：US06080646A
公开(公告)日：2000-06-27
申请号：US81423
申请日：1998-05-20
申请人： Kun-Chih Wang
发明人： Kun-Chih Wang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/28079 , H01L29/495
摘要： A method of fabricating a MOS transistor having an aluminum gate is disclosed. On a MOS transistor having a polysilicon gate, an insulating layer is first formed. The device surface is then polished by CMP to expose the polysilicon gate. Then, an aluminum layer is formed on the substrate and then processed through annealing at more than 500.degree. C. so that a portion of the aluminum layer substitutes the polysilicon gate to form an aluminum gate. After removing the substituted polysilicon and the non-reacted aluminum, the NMOS transistor with an aluminum gate is completed.
摘要翻译：公开了一种制造具有铝栅极的MOS晶体管的方法。在具有多晶硅栅极的MOS晶体管上，首先形成绝缘层。然后通过CMP抛光器件表面以暴露多晶硅栅极。然后，在基板上形成铝层，然后通过在500℃以上的退火进行处理，使得铝层的一部分代替多晶硅栅极形成铝栅极。在去除取代的多晶硅和未反应的铝之后，完成具有铝栅极的NMOS晶体管。

16. 发明授权

US07562539B2 Method and the device for making high precision coating of insert for glass molding 失效
标题翻译：玻璃成型用插入件高精度涂层方法及装置
公开(公告)号：US07562539B2
公开(公告)日：2009-07-21
申请号：US11011130
申请日：2004-12-15
申请人： Kun-Chih Wang
发明人： Kun-Chih Wang
IPC分类号： C03B40/00
CPC分类号： C03C17/001 , C03B11/086 , C03B27/02 , C03C2218/15 , Y02P40/57
摘要： A method for making high precision hard film coating on a mold core comprises the following steps of: (a) providing a mold jig (200, 300) and a mold core (208, 308); (b) defining a through hole (206, 364) of a first inner diameter in the mold jig; (c) forming a rim (254, 354) of a second inner diameter on the inner side of the through hole, the second inner diameter being smaller than the first inner diameter; (d) configuring the mold core into a mold core including a body (212, 312) of a first external diameter and a top portion (250, 350) of a second external diameter, the second external diameter being smaller than the first external diameter to define a shoulder (252, 352) between the body and the top portion, the first external diameter being substantially equal to the first inner diameter and larger than the second inner diameter, the second external diameter being substantially equal to or smaller than the second inner diameter; and (e) coreing the mold core into the through hole of the mold jig from the bottom, the shoulder of the mold core engaging with the rim, the upper surface of the top portion of the mold core being substantially flush with the upper surface of the mold jig, and a groove (256, 356) being defined between the inner side of the through hole and the outer side of the top portion of the mold core. A device for performing this method is also disclosed.
摘要翻译：在模芯上制造高精度硬膜的方法包括以下步骤：（a）提供模具夹具（200,300）和模芯（208,308）; （b）在所述模具夹具中限定第一内径的通孔（206,364）; （c）在所述通孔的内侧上形成第二内径的边缘（254,354），所述第二内径小于所述第一内径; （d）将模芯配置成包括第一外径的主体（212,312）和第二外径的顶部（250,350）的模芯，所述第二外径小于所述第一外径以限定主体和顶部之间的肩部（252,352），第一外径基本上等于第一内径并且大于第二内径，第二外径基本上等于或小于第二内径内径; 和（e）将模芯从底部夹入模具夹具的通孔中，模芯的凸缘与边缘接合，模芯顶部的上表面基本上与模具夹具和在通孔的内侧和模芯的顶部的外侧之间限定的凹槽（256,356）。还公开了一种用于执行该方法的装置。

17. 发明授权

US07372168B2 Semiconductor chip capable of implementing wire bonding over active circuits 有权
标题翻译：能够在有源电路上实现引线键合的半导体芯片
公开(公告)号：US07372168B2
公开(公告)日：2008-05-13
申请号：US11379572
申请日：2006-04-21
申请人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
发明人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/53228 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.
摘要翻译：提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘和顶部互连金属层之间的第一通孔塞。半导体芯片还至少包括互连金属层，在互连金属层和焊盘结构之间的至少第二通孔插塞以及位于半导体衬底上的焊盘结构下方的有源电路。

18. 发明授权

US07208837B2 Semiconductor chip capable of implementing wire bonding over active circuits 有权
公开(公告)号：US07208837B2
公开(公告)日：2007-04-24
申请号：US10907959
申请日：2005-04-22
申请人： Kun-Chih Wang , Bing-Chang Wu
发明人： Kun-Chih Wang , Bing-Chang Wu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/53238 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , Y10T428/24917 , Y10T428/265 , H01L2924/00014
摘要： A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.

19. 发明申请

US20070010122A1 Miniaturized lens assembly and method for making the same 审中-公开
标题翻译：小型化镜头组件及其制造方法
公开(公告)号：US20070010122A1
公开(公告)日：2007-01-11
申请号：US11439117
申请日：2006-05-24
申请人： Kun-Chih Wang
发明人： Kun-Chih Wang
IPC分类号： H01R13/627 , B29D11/00
CPC分类号： B29D11/0073
摘要： A miniaturized lens assembly includes an image-capturing unit, a lens unit, and a binding layer. The image-capturing unit includes an image-capturing member. The lens unit includes an image-projecting portion for projecting an image along an optical axis to the image-capturing member. The binding layer extends around the optical axis, and binds the image-capturing unit to the lens unit. The binding layer includes a photosensitive polymeric material and spaces apart the lens unit and the image-capturing unit. A method for making the miniaturized lens assembly is also disclosed.
摘要翻译：小型化透镜组件包括图像捕获单元，透镜单元和粘结层。图像捕获单元包括图像捕获构件。透镜单元包括用于将图像沿着光轴投射到图像捕获构件的图像投影部分。绑定层围绕光轴延伸，并且将图像捕获单元绑定到透镜单元。粘合层包括光敏聚合物材料，并且使透镜单元和图像捕获单元分开。还公开了一种用于制造小型化透镜组件的方法。

20. 发明申请

US20060026995A1 Molding core and method for making the same 审中-公开
标题翻译：成型芯和制造方法
公开(公告)号：US20060026995A1
公开(公告)日：2006-02-09
申请号：US11152277
申请日：2005-06-13
申请人： Kun-Chih Wang
发明人： Kun-Chih Wang
IPC分类号： C03B11/08
CPC分类号： C03B11/086 , C03B2215/12 , C03B2215/26 , C03B2215/31 , C03B2215/32 , C03B2215/34 , C23C16/0272 , C23C16/26
摘要： A molding core includes: a core body having an article-shaping surface; and a hard coating formed on the article-shaping surface of the core body and including a diamond-like carbon film that includes carbon, nitrogen, and at least one bonding-enhancing element which is selected from silicon, titanium, aluminum, tungsten, tantalum, chromium, zirconium, vanadium, niobium, hafnium, and boron, and which forms covalence bonding with the carbon and the nitrogen.
摘要翻译：成形芯包括：具有制品成形表面的芯体; 以及形成在芯体的制品成形表面上的硬质涂层，并且包括包含碳，氮和至少一种选自硅，钛，铝，钨，钽的粘合增强元素的类金刚石碳膜，铬，锆，钒，铌，铪和硼，并且与碳和氮键合形成共价。

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