专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06334311B1 Thermoelectric-cooling temperature control apparatus for semiconductor device fabrication facility 失效
标题翻译：用于半导体器件制造设备的热电冷却温度控制装置
公开(公告)号：US06334311B1
公开(公告)日：2002-01-01
申请号：US09511896
申请日：2000-02-23
申请人： Tae-hoon Kim , Byung-chul Kim , Young-woo Lee , Tae-ryong Kim
发明人： Tae-hoon Kim , Byung-chul Kim , Young-woo Lee , Tae-ryong Kim
IPC分类号： F25B2102
CPC分类号： H01L35/32 , F25B21/02 , H01L35/30 , Y02P80/156
摘要： A thermoelectric-cooling temperature control apparatus for a semiconductor device fabrication facility maintains a temperature condition, such as the temperature of a wafer, stable during the fabrication process. The apparatus includes a heat exchanger having a thermoelectric cooling element which produces a Peltier Effect to cause the element to absorb and radiate heat according to current flowing through the element
摘要翻译：用于半导体器件制造设备的热电冷却温度控制装置在制造过程中保持诸如晶片的温度的温度条件稳定。该装置包括具有热电冷却元件的热交换器，该热电冷却元件产生珀耳帖效应，以使元件根据流过元件的电流吸收和辐射热量

12. 发明授权

US09123994B2 Antenna structure 有权
标题翻译：天线结构
公开(公告)号：US09123994B2
公开(公告)日：2015-09-01
申请号：US13482453
申请日：2012-05-29
申请人： Young-ju Lee , Byung-chul Kim , Jung-min Park
发明人： Young-ju Lee , Byung-chul Kim , Jung-min Park
IPC分类号： H01Q1/36 , H01Q1/22 , H01Q1/24 , H01Q1/38 , H01Q1/52 , H01Q9/04
CPC分类号： H01Q1/36 , H01Q1/2291 , H01Q1/243 , H01Q1/38 , H01Q1/52 , H01Q9/0414
摘要： An antenna structure includes: a substrate; a ground layer disposed on a first surface of the substrate; a patch antenna unit which is disposed on a second surface of the substrate opposite to the first surface of the substrate, and is configured to receive a signal to be radiated; and a three-dimensional (3D) antenna unit which comprises a shorting leg that is shorted with the patch antenna unit, and is configured to radiate the signal received by the patch antenna unit.
摘要翻译：天线结构包括：基板; 设置在所述基板的第一表面上的接地层; 贴片天线单元，设置在与基板的第一表面相对的基板的第二表面上，并且被配置为接收要辐射的信号; 以及三维（3D）天线单元，其包括与所述贴片天线单元短路的短路支路，并且被配置为辐射由所述贴片天线单元接收的信号。

13. 发明授权

US08339883B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08339883B2
公开(公告)日：2012-12-25
申请号：US12948302
申请日：2010-11-17
申请人： Je-min Yu , Byung-chul Kim , Jun-hyung Kim , Sang-joon Hwang
发明人： Je-min Yu , Byung-chul Kim , Jun-hyung Kim , Sang-joon Hwang
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C11/4094 , G11C11/4097 , G11C2207/002
摘要： A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging unit precharging the pair of local datalines to a precharging voltage level in response to a precharging signal, and a dataline sensing amp detecting and amplifying data transmitted to the pair of local datalines. The dataline sensing amp includes a charge sync unit discharging the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and data of the pair of local datalines, and a data sensing unit transmitting data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.
摘要翻译：半导体存储器件包括：位线检测放大器，用于检测和放大来自存储器单元的一对位线的数据;列选择单元，响应于列选择信号，将一对位线的数据传输到一对本地数据; 数据预充电单元响应于预充电信号将一对本地数据线预充电到预充电电压电平，以及数据感测放大器检测和放大传输到该对本地数据线的数据。数据传感放大器包括电荷同步单元，响应于第一数据感测使能信号和一对本地数据的数据，以预充电电压电平放电该对本地数据线;以及数据感测单元，传输该对本地数据响应于第二数据感测使能信号将数据传送到一对全局数据。

14. 发明授权

US08313905B2 Detection oligomer and method for controlling quality of biochip using detection oligomer 失效
标题翻译：检测低聚物和使用检测低聚物控制生物芯片质量的方法
公开(公告)号：US08313905B2
公开(公告)日：2012-11-20
申请号：US12358530
申请日：2009-01-23
申请人： Joo-Won Rhee , Byung-chul Kim , Sun-Ok Jung , Seung-Hei Cho
发明人： Joo-Won Rhee , Byung-chul Kim , Sun-Ok Jung , Seung-Hei Cho
IPC分类号： C12Q1/68 , C12P19/34 , C07H21/02
CPC分类号： C12Q1/6837 , C12Q2525/301 , C12Q2525/131 , C12Q2521/501
摘要： A detection oligomer and method for controlling the quality of a biochip using the detection oligomer are provided. The detection oligomer includes a template having a first and second end and having a sequence that is complementary to a specific sequence of an oligomer, and a hairpin connected to the first end of the template.
摘要翻译：提供了使用检测低聚物来控制生物芯片的质量的检测低聚物和方法。检测低聚物包括具有第一和第二末端并具有与寡聚体的特定序列互补的序列的模板和连接到模板的第一端的发夹。

15. 发明授权

US07857141B2 Apparatus and method for separating components 有权
标题翻译：用于分离组件的装置和方法
公开(公告)号：US07857141B2
公开(公告)日：2010-12-28
申请号：US11850258
申请日：2007-09-05
申请人： Jong-myeon Park , Byung-chul Kim
发明人： Jong-myeon Park , Byung-chul Kim
IPC分类号： B03B5/60 , B03D1/00
CPC分类号： B01L3/50273 , B01L3/502738 , B01L3/502753 , B01L2300/0806 , B01L2300/0864 , B01L2300/1861 , B01L2400/0409 , B01L2400/0677 , F16K99/0001 , F16K99/0021 , F16K99/0063 , F16K2099/0074 , F16K2099/0076 , F16K2099/0084 , G01N21/07
摘要： An apparatus for separating components and a method of separating components using the apparatus are provided. The apparatus includes: a main chamber which contains a sample that is separated into a plurality of layers by a centrifugal force; a component separating chamber which is connected to the main chamber, and receives a specific layer including specific components among the plurality of layers; a first channel which connects the component separating chamber to the main chamber; and a first channel valve which is disposed in the first channel to control a liquid flowing through the first channel.
摘要翻译：提供了一种用于分离组件的装置和使用该装置分离组件的方法。该装置包括：主室，其包含通过离心力分离成多个层的样品; 分离室，其连接到所述主室，并且在所述多个层中接收包括特定成分的特定层; 将部件分离室连接到主室的第一通道; 以及第一通道阀，其设置在第一通道中以控制流过第一通道的液体。

16. 发明申请

US20060273377A1 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20060273377A1
公开(公告)日：2006-12-07
申请号：US11504702
申请日：2006-08-16
申请人： Hee-soon Chae , Chung-woo Kim , Kwang-youl Seo , Tae-hyun Han , Byung-chul Kim , Joo-yeon Kim
发明人： Hee-soon Chae , Chung-woo Kim , Kwang-youl Seo , Tae-hyun Han , Byung-chul Kim , Joo-yeon Kim
IPC分类号： H01L29/788
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/7887
摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.
摘要翻译：提供一种非易失性存储器件及其制造方法。该器件包括半导体衬底; 设置在所述半导体衬底中的源区和漏区以及置于所述源极和漏极区之间的沟道区; 设置在所述源极区附近的所述沟道区上的第一隧道氧化物层; 设置在漏区附近的沟道区上的第二隧道氧化层; 设置在第一隧道氧化物层上的第一电荷俘获层; 设置在所述第二隧道氧化物层上的第二电荷俘获层; 覆盖第一和第二电荷俘获层的阻挡氧化物层; 介于所述第一和第二电荷俘获层之间的电荷隔离层; 以及设置在阻挡氧化物层上的栅电极。

17. 发明申请

US20050114064A1 Circuit for a parallel bit test of a semiconductor memory device and method thereof 审中-公开
标题翻译：半导体存储器件的并行位测试电路及其方法
公开(公告)号：US20050114064A1
公开(公告)日：2005-05-26
申请号：US10911503
申请日：2004-08-05
申请人： Joo-weon Shin , Byung-chul Kim , Seung-bum Ko , Soo-in Cho
发明人： Joo-weon Shin , Byung-chul Kim , Seung-bum Ko , Soo-in Cho
IPC分类号： G11C29/00 , G01D3/00 , G11C29/34
CPC分类号： G11C29/34 , G11C2029/2602
摘要： A method for performing a parallel bit test of a semiconductor memory device, including writing data to each of a plurality of memory cells, reading data from each of the plurality of memory cells, testing the data from each of the plurality of memory cells in a first test mode, and testing the data from each of the plurality of memory cells in a second test mode. A circuit including a first test mode circuit for receiving first data, a second test mode circuit for receiving second data, and wherein the first test mode circuit tests the received first data and the second test mode tests the received second data. Another circuit including a first comparator with a plurality of comparison circuits, a test mode selector for selecting at least one of a plurality of outputs from the first comparator, and a second comparator for receiving the selected output.
摘要翻译：一种用于执行半导体存储器件的并行位测试的方法，包括将数据写入多个存储器单元中的每一个，从多个存储器单元中的每一个读取数据，在多个存储单元中的每一个存储单元中测试数据第一测试模式，并且在第二测试模式中测试来自多个存储器单元中的每一个的数据。一种电路，包括用于接收第一数据的第一测试模式电路，用于接收第二数据的第二测试模式电路，并且其中第一测试模式电路测试接收的第一数据，第二测试模式测试接收的第二数据。另一个电路包括具有多个比较电路的第一比较器，用于选择来自第一比较器的多个输出中的至少一个的测试模式选择器，以及用于接收所选输出的第二比较器。

18. 发明授权

US06442717B1 Parallel bit testing circuits and methods for integrated circuit memory devices including shared test drivers 失效
标题翻译：用于集成电路存储器件的并行位测试电路和方法，包括共享测试驱动器
公开(公告)号：US06442717B1
公开(公告)日：2002-08-27
申请号：US09274706
申请日：1999-03-23
申请人： Byung-chul Kim
发明人： Byung-chul Kim
IPC分类号： G11C2900
CPC分类号： G11C29/12
摘要： Integrated circuit memory device testing circuits and methods compare data on a selected number of the data line outputs of a memory cell array to one another to produce comparison results, in response to a selection signal that indicates the selected number of the data line outputs to be compared to one another. A shared test driver is responsive to the comparison circuit to provide the comparison results to an associated global output line for at least two values of the selection signal that indicate at least two selected numbers of data line outputs to be compared to one another. By sharing test drivers, separate test drivers need not be provided for each selected number of the data line outputs that are compared to one another. The number of test drivers may therefore be reduced so that the area occupied by the testing circuits may be reduced.
摘要翻译：集成电路存储器件测试电路和方法将存储器单元阵列的选定数量的数据线输出端上的数据彼此进行比较，以产生比较结果，以响应于选择信号，该选择信号指示所选数量的数据线输出为相比之下。共享测试驱动器响应于比较电路，以将比较结果提供给选择信号的至少两个值的关联全局输出线，该至少两个值指示要彼此比较的至少两个选定数量的数据线输出。通过共享测试驱动程序，不需要为彼此进行比较的每个选定数量的数据线输出提供单独的测试驱动程序。因此，可以减少测试驱动器的数量，从而可以减少测试电路占据的面积。

19. 发明授权

US08307988B2 Apparatus and method for separating components 失效
标题翻译：用于分离组件的装置和方法
公开(公告)号：US08307988B2
公开(公告)日：2012-11-13
申请号：US12952208
申请日：2010-11-23
申请人： Jong-myeon Park , Byung-chul Kim
发明人： Jong-myeon Park , Byung-chul Kim
IPC分类号： B03B5/60
CPC分类号： G01N21/07 , B01L3/50273 , B01L3/502738 , B01L3/502753 , B01L2300/0806 , B01L2300/0864 , B01L2300/1861 , B01L2400/0409 , B01L2400/0677 , F16K99/0001 , F16K99/0021 , F16K99/0063 , F16K2099/0074 , F16K2099/0076 , F16K2099/0084 , Y10T436/111666 , Y10T436/25375
摘要： An apparatus for separating components and a method of separating components using the apparatus are provided. The apparatus includes: a main chamber which contains a sample that is separated into a plurality of layers by a centrifugal force; a component separating chamber which is connected to the main chamber, and receives a specific layer including specific components among the plurality of layers; a first channel which connects the component separating chamber to the main chamber; and a first channel valve which is disposed in the first channel to control a liquid flowing through the first channel.
摘要翻译：提供了一种用于分离组件的装置和使用该装置分离组件的方法。该装置包括：主室，其包含通过离心力分离成多个层的样品; 分离室，其连接到所述主室，并且在所述多个层中接收包括特定成分的特定层; 将部件分离室连接到主室的第一通道; 以及第一通道阀，其设置在第一通道中以控制流过第一通道的液体。

20. 发明授权

US08263333B2 Method of analyzing a target nucleic acid sequence 有权
标题翻译：分析靶核酸序列的方法
公开(公告)号：US08263333B2
公开(公告)日：2012-09-11
申请号：US12644295
申请日：2009-12-22
申请人： Byung-chul Kim
发明人： Byung-chul Kim
IPC分类号： C12Q1/68 , C12P19/34 , C07H21/02 , C07H21/04
CPC分类号： C12Q1/6869 , C12Q2525/301 , C12Q2565/501
摘要： Provided is a method of analyzing a target nucleic acid sequence by using an elongation reaction and a ligation reaction.
摘要翻译：提供了通过使用延伸反应和连接反应来分析靶核酸序列的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式