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11. 发明申请

US20050212606A1 Wireless communications device having type-II all-digital phase-locked loop (PLL) 有权
标题翻译：具有II型全数字锁相环（PLL）的无线通信设备
公开(公告)号：US20050212606A1
公开(公告)日：2005-09-29
申请号：US11122670
申请日：2005-05-04
申请人： Robert Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03F1/02 , H03F1/32 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/00
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

12. 发明申请

US20050130618A1 Sampling mixer with asynchronous clock and signal domains 有权
标题翻译：具有异步时钟和信号域的采样混频器
公开(公告)号：US20050130618A1
公开(公告)日：2005-06-16
申请号：US11028995
申请日：2005-01-03
申请人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H03D7/12 , H04B1/10 , H04B1/06 , H04B7/00 , H04L7/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译：具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。利用混频器中不同采样电容器之间的显着电容差和叠加特性。

13. 发明申请

US20050104654A1 Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权
标题翻译：使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术
公开(公告)号：US20050104654A1
公开(公告)日：2005-05-19
申请号：US10712593
申请日：2003-11-13
申请人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
IPC分类号： H03B1/00 , H03H19/00 , H04B1/10
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译：改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

14. 发明申请

US20060135107A1 Removing close-in interferers through a feedback loop 有权
标题翻译：通过反馈回路消除紧密的干扰源
公开(公告)号：US20060135107A1
公开(公告)日：2006-06-22
申请号：US11339386
申请日：2006-01-25
申请人： Robert Staszewski , Khurram Muhammad , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Dirk Leipold
IPC分类号： H04B1/10
CPC分类号： H04B1/28 , H04B1/1036
摘要： System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.
摘要翻译：通过反馈消除接近干扰的系统和方法。优选实施例包括耦合到直接RF无线电接收机（例如，无线电接收机800）的数字输出的干扰源预测器（例如，干扰源预测器840）。干扰源预测器预测干扰源的存在，并且通过使用电荷共享通过反馈电路（例如，反馈单元845）将信息反馈给采样单元（例如，采样单元805）。然后在采样单元中消除干扰源。另外，通过执行任意系数有限脉冲响应滤波器来增加和改变采样单元滤波器中的零数和位置。

15. 发明申请

US20050233725A1 Image reject filtering in a direct sampling mixer 审中-公开
标题翻译：直接采样混频器中的图像抑制滤波
公开(公告)号：US20050233725A1
公开(公告)日：2005-10-20
申请号：US10828386
申请日：2004-04-20
申请人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
IPC分类号： H03D7/18 , H03H19/00 , H04B1/16 , H04B1/28
CPC分类号： H03D7/18 , H03H19/004 , H03H2007/0192
摘要： Disclosed are methods, circuits and systems for image reject filtering in a multi-tap direct sampling mixer (MTDSM) of an IF or RF system. Disclosed is the use of rotating capacitors among the in-phase and quadrature branches of a signal processing system. The exchange of information among the branches of the I and Q channels is used in the implementation of a complex filter. Embodiments using cascaded multiple stages of the complex filter to provide higher order complex filters are also disclosed.
摘要翻译：公开了用于IF或RF系统的多抽头直接采样混频器（MTDSM）中的图像抑制滤波的方法，电路和系统。公开了在信号处理系统的同相和正交分支中使用旋转电容器。在I和Q通道的分支之间的信息交换被用于实现复杂的过滤器。还公开了使用复合滤波器的级联多级以提供更高阶复数滤波器的实施例。

16. 发明申请

US20060256910A1 FAST HOPPING FREQUENCY SYNTHESIZER USING AN ALL DIGITAL PHASED LOCKED LOOP (ADPLL) 有权
标题翻译：使用所有数字相位锁定环路（ADPLL）快速搜寻频率合成器
公开(公告)号：US20060256910A1
公开(公告)日：2006-11-16
申请号：US11382570
申请日：2006-05-10
申请人： Nir Tal , Robert Staszewski , Ofer Friedman
发明人： Nir Tal , Robert Staszewski , Ofer Friedman
IPC分类号： H04B1/00 , H03D3/24 , H04B1/713
CPC分类号： H04B1/7136 , H03C3/40 , H03D3/007 , H03L7/08 , H03L7/0991 , H04B1/71635 , H04B1/71637 , H04B2001/71365
摘要： A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/fT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency. A mixer applies the waveform to the I and Q data samples prior to conversion to the digital domain.
摘要翻译：一种新颖有用的快速频率合成器和发射机。频率合成器和发射器包含适用于操作开环的数字控制振荡器（DCO）。通过改变振荡器调谐字（OTW）来模拟UWB发射机的三个振荡器来实现瞬时频率切换。在一个实施例中，DCO可以在用于构造DCO的变容二极管装置的1 / f T T中瞬时改变频率。在数据包发送或接收开始之前，全数字锁相环（ADPLL）用于离线校准。开关期间的任何相移都由发射机中的数字电路跟踪。在第二实施例中，通过使用有效地产生有效地移动合成频率的精细分辨率复指数波形的数控振荡器（NCO）来提供额外的频率精度。混频器在转换为数字域之前将波形应用于I和Q数据采样。

17. 发明申请

US20050287967A1 Low noise high isolation transmit buffer gain control mechanism 有权
标题翻译：低噪声高隔离传输缓冲器增益控制机制
公开(公告)号：US20050287967A1
公开(公告)日：2005-12-29
申请号：US11115815
申请日：2005-04-26
申请人： Chih-Ming Hung , Francis Cruise , Dirk Leipold , Robert Staszewski
发明人： Chih-Ming Hung , Francis Cruise , Dirk Leipold , Robert Staszewski
IPC分类号： H01Q11/12 , H03F1/32 , H03F3/191 , H04B1/04
CPC分类号： H04B1/0483 , H03F1/3241 , H03F1/3294 , H03F3/191 , H03F2200/331
摘要： A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.
摘要翻译：一种低噪声，高隔离，全数字发送缓冲增益控制机制的新型设备。增益控制方案在全数字直接数/频幅度转换器（DRAC）的上下文中呈现，该转换器有效地结合了上变频，I和Q组合，D / A转换，滤波，缓冲和 RF输出幅度控制成单个电路。发送缓冲器构造为NMOS开关阵列。每个NMOS开关的控制逻辑包括一个通门型AND门，其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。通过在CMOS工艺中实现时，通过识别伪E类预功率放大器（PPA）所遭受的损伤来实现功率控制。首先，阵列的NMOS开关具有大的导通电阻，因此当输入波形为高时，只能从RF扼流圈画出有限的电流。在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制，并允许控制RF输出功率的全数字方法。

18. 发明授权

US09419635B2 Time-to-digital converter and method therefor 有权
标题翻译：时 - 数转换器及其方法
公开(公告)号：US09419635B2
公开(公告)日：2016-08-16
申请号：US14343932
申请日：2012-09-10
申请人： Priyanka Kumar , Robert Staszewski , Edoardo Charbon
发明人： Priyanka Kumar , Robert Staszewski , Edoardo Charbon
IPC分类号： G01B11/24 , H03M1/00 , G01T1/164 , G04F10/00 , H04N5/378 , H04N13/02
CPC分类号： H03M1/002 , G01B11/24 , G01T1/1647 , G04F10/005 , H04N5/378 , H04N13/20 , H04N2213/001
摘要： 3D imager including at least one pixel, each pixel including a photodetector for detecting photon incidence and a time-to-digital converter system configured for referencing the photon incidence to a reference clock, and further including a reference clock generator provided for generating the reference clock, wherein the reference clock generator is configured for adjusting the frequency of the reference clock on the basis of an estimated time up to a subsequent photon incidence.
摘要翻译： 3D成像器包括至少一个像素，每个像素包括用于检测光子入射的光电检测器和配置用于参考光子入射到参考时钟的时间数字转换器系统，并且还包括参考时钟发生器，用于产生参考时钟，其中所述参考时钟发生器被配置为基于直到随后的光子入射的估计时间来调整所述参考时钟的频率。

19. 发明申请

US20080061892A1 Single-Electron Injection/Extraction Device for a Resonant Tank Circuit and Method of Operation Thereof 有权
标题翻译：用于谐振槽电路的单电子注入/提取装置及其操作方法
公开(公告)号：US20080061892A1
公开(公告)日：2008-03-13
申请号：US11846987
申请日：2007-08-29
申请人： Robert Staszewski , Renaldi Winoto , Dirk Leipold
发明人： Robert Staszewski , Renaldi Winoto , Dirk Leipold
IPC分类号： H03B28/00 , H04B1/40
CPC分类号： H03B1/04 , H03B5/12 , H03B2202/027 , H03B2202/076
摘要： A system for reducing phase-noise in a resonant tank circuit. The system includes a single-electron device configured to inject a single electron into the oscillator circuit tank circuit. The system further includes a synchronizer coupled to the single-electron device and configured to cause the single-electron device to inject the single electron into the resonant tank circuit at a phase based on an extreme (maximum or minimum) electrical characteristic output of the resonant tank circuit.
摘要翻译：一种降低谐振回路中相位噪声的系统。该系统包括被配置为将单个电子注入到振荡器电路槽电路中的单电子器件。该系统还包括耦合到单电子器件并被配置为使得单电子器件基于谐振的极端（最大或最小）电特性输出的相位将单个电子注入到谐振回路中的同步器坦克回路。

20. 发明申请

US20070110194A1 METHOD OF DEFINING SEMICONDUCTOR FABRICATION PROCESS UTILIZING TRANSISTOR INVERTER DELAY PERIOD 有权
标题翻译：定义半导体制造工艺的方法利用晶体管逆变器延迟时间
公开(公告)号：US20070110194A1
公开(公告)日：2007-05-17
申请号：US11550878
申请日：2006-10-19
申请人： Elida de Obaldia , Robert Staszewski , Dirk Leipold
发明人： Elida de Obaldia , Robert Staszewski , Dirk Leipold
IPC分类号： H04L27/08 , H03L7/00
CPC分类号： H04L27/361 , H03L7/091 , H03L7/0991 , H03L7/1806
摘要： A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The method and apparatus provide direct measurement of fabrication process variation in circuits without requiring any additional test equipment by utilizing a time to digital converter (TDC) circuit already present in the chip. The TDC circuit relies on the time delay in an inverter chain to sample a high speed CKV clock using a slow FREF clock. Calculation of inverse time provides a direct correlation for fabrication process variation in each die.
摘要翻译：一种用于定义数字RF处理器（DRP）中的处理变化的新颖方法和装置。本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。该方法和装置提供对电路中制造工艺变化的直接测量，而不需要使用已经存在于芯片中的时间 - 数字转换器（TDC）电路的任何额外的测试设备。 TDC电路依赖于逆变器链中的时间延迟，使用缓慢的FREF时钟采样高速CKV时钟。逆时间的计算提供了每个模具中制造工艺变化的直接相关性。

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