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11. 发明申请

US20050114735A1 Systems and methods for verifying core determinacy 审中-公开
标题翻译：验证核心确定性的系统和方法
公开(公告)号：US20050114735A1
公开(公告)日：2005-05-26
申请号：US10718123
申请日：2003-11-20
申请人： Zachary Smith , Kevin Safford , Jeremy Petsinger
发明人： Zachary Smith , Kevin Safford , Jeremy Petsinger
IPC分类号： G02B5/10 , G06F11/00 , G06F17/50
CPC分类号： G06F17/5022
摘要： In one embodiment, a core determinacy verification system and a method pertain to extracting data stored in core model structures, comparing the extracted data of one modeled processor core with extracted data of another modeled processor core, determining if any mismatching data will cause core divergence, and facilitating notice of an error if any mismatching data will cause core divergence.
摘要翻译：在一个实施例中，核心确定性验证系统和方法涉及提取存储在核心模型结构中的数据，将提取的一个建模的处理器核心的数据与另一建模的处理器核心的提取数据进行比较，确定是否有任何不匹配的数据将导致核心发散，并且如果任何不匹配的数据将导致核心分歧，便于通知错误。

12. 发明申请

US20070043929A1 System and method for responding to TLB misses 失效
标题翻译：用于响应TLB未命中的系统和方法
公开(公告)号：US20070043929A1
公开(公告)日：2007-02-22
申请号：US11205622
申请日：2005-08-17
申请人： Kevin Safford , Rohit Bhatia , Karl Brummel
发明人： Kevin Safford , Rohit Bhatia , Karl Brummel
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/1018
摘要： The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.
摘要翻译：本发明涉及一种改进的微处理器，具有具有多个可以操作以提供虚拟存储器的高速缓存的存储器系统。在微处理器中包括的高速缓冲存储器中的是传统的高速缓冲存储器，其存储由微处理器执行的处理使用的数据和指令，并且通常被布置在高速缓存层级中，以及一个或多个转换后备缓冲器（TLB）高速缓存它存储有限数量的虚拟页面翻译。改进的微处理器还具有额外的高速缓存，用于存储当TLB未命中时被访问的虚拟散列页表（VHPT）。引入这种VHPT高速缓存消除或者至少减少了当TLB未命中时微处理器在高速缓存层级的高速缓存或微处理器外部的其他存储器（例如，主存储器）中查找信息的需要，从而增强了微处理器速度。

13. 发明申请

US20060036424A1 Method and apparatus for verifying resources shared by multiple processors 审中-公开
标题翻译：用于验证由多个处理器共享的资源的方法和装置
公开(公告)号：US20060036424A1
公开(公告)日：2006-02-16
申请号：US10917764
申请日：2004-08-13
申请人： Jeremy Petsinger , Danny Kwong , Kevin Safford
发明人： Jeremy Petsinger , Danny Kwong , Kevin Safford
IPC分类号： G06F13/10
CPC分类号： G06F9/52 , G06F12/084
摘要： Computer system models and methods for modeling computers that share resources are disclosed herein. One embodiment of the method for modeling a computer system comprises modeling a first shared resource and associating a first model of the first shared resource with a first processor model. A second model of the first shared resource is associated with a second processor model, wherein the first model of the first shared resource is substantially identical to the second model of the first shared resource. Data associated with the first model of the first shared resource is maintained to be equal to the data associated with the second model of the first shared resource.
摘要翻译：本文公开了用于建模共享资源的计算机的计算机系统模型和方法。用于建模计算机系统的方法的一个实施例包括对第一共享资源进行建模并将第一共享资源的第一模型与第一处理器模型相关联。第一共享资源的第二模型与第二处理器模型相关联，其中第一共享资源的第一模型基本上与第一共享资源的第二模型相同。与第一共享资源的第一模型相关联的数据被保持为等于与第一共享资源的第二模型相关联的数据。

14. 发明申请

US20060248384A1 Method and apparatus for recovery from loss of lock step 有权
公开(公告)号：US20060248384A1
公开(公告)日：2006-11-02
申请号：US11454087
申请日：2006-06-16
申请人： Kevin Safford
发明人： Kevin Safford
IPC分类号： G06F11/00
CPC分类号： G06F11/2038 , G06F11/1641 , G06F11/165 , G06F11/1658 , G06F11/2025 , G06F2201/845
摘要： An apparatus, operating on an advanced multi-core processor architecture, and a corresponding method, are used to enhance recovery from loss of lock step in a multi-processor computer system. The apparatus for recovery from loss of lock step includes multiple processor units operating in the computer system, each of the processor units having at least two processor units operating in lock step, and at least one idle processor unit operating in lock step; and a controller coupled to the two processor units operating in lock step and the idle processor unit. The controller includes mechanisms for copying an architected state of each of the two lock step processor units to the idle processor unit.

15. 发明申请

US20130275787A1 Methods And Apparatuses For Reducing Step Loads Of Processors 审中-公开
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US20130275787A1
公开(公告)日：2013-10-17
申请号：US13913864
申请日：2013-06-10
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

16. 发明申请

US20090070607A1 Methods and apparatuses for reducing step loads of processors 有权
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US20090070607A1
公开(公告)日：2009-03-12
申请号：US11900316
申请日：2007-09-11
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

17. 发明申请

US20070061812A1 Method and apparatus for communicating information between lock stepped processors 有权
标题翻译：用于在锁步阶处理器之间传递信息的方法和装置
公开(公告)号：US20070061812A1
公开(公告)日：2007-03-15
申请号：US11598781
申请日：2006-11-14
申请人： Kevin Safford , Jeremy Petsinger
发明人： Kevin Safford , Jeremy Petsinger
IPC分类号： G06F9/46
CPC分类号： G06F11/1683 , G06F9/30189 , G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F11/1641
摘要： An apparatus for communicating between lock step is incorporated on two or more processors operating in a lock step mode. Each of the processors includes processor logic to execute a code sequence, and an identical code sequence is executed by the processor logic. The apparatus further includes a processor-specific resource referenced by the code sequence. A multiplexer is coupled to the processor-specific resource, and is controlled to read data based on the identification. Coupled to the processors is a lock step logic block operable to read and compare the output of each of the processors. The lock step logic determines if operation of the processors is in a lock step mode or in an independent processor mode. Such determination may be made by the lock step logic turning off, for example.
摘要翻译：用于锁定步骤之间的通信的装置被结合在以锁定步骤模式操作的两个或多个处理器上。每个处理器包括执行代码序列的处理器逻辑，并且处理器逻辑执行相同的代码序列。该装置还包括由代码序列引用的特定于处理器的资源。多路复用器耦合到特定于处理器的资源，并被控制以基于识别来读取数据。耦合到处理器的是锁步骤逻辑块，可操作以读取和比较每个处理器的输出。锁定步骤逻辑确定处理器的操作是处于锁定步骤模式还是处于独立处理器模式。例如，可以通过锁定步骤逻辑关闭来进行这种确定。

18. 发明申请

US20060085677A1 Method and apparatus for seeding differences in lock-stepped processors 失效
标题翻译：在锁阶处理器中播种差异的方法和装置
公开(公告)号：US20060085677A1
公开(公告)日：2006-04-20
申请号：US11290504
申请日：2005-12-01
申请人： Kevin Safford , Jeremy Petsinger
发明人： Kevin Safford , Jeremy Petsinger
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F9/52
摘要： An apparatus, and a corresponding method, are used for seeding differences in lock stepped processors, the apparatus implemented on two or more processors operating in a lock step mode. Each of the two or more processors comprise a processor-specific resource operable to seed the differences, a processor logic to execute a code sequence, in which an identical code sequence is executed by the processor logic of each of the two or more processors, and an output to provide a result of execution of the code sequence. The processor outputs, based on execution of the code sequence is provided to a lock step logic operable to read and compare the output of each of the two or more processors.
摘要翻译：一种装置和相应的方法用于锁定步进式处理器的种子差异，该装置在两个或多个处理器上实现，该处理器以锁步骤模式运行。两个或更多个处理器中的每一个包括可操作以对差异进行种子化的处理器专用资源，处理器逻辑以执行代码序列，其中由两个或多个处理器中的每一个的处理器逻辑执行相同的代码序列，以及用于提供执行代码序列的结果的输出。基于代码序列的执行，处理器输出被提供给可操作以读取和比较两个或更多个处理器中的每一个的输出的锁定步骤逻辑。

19. 发明申请

US20050240793A1 Architectural support for selective use of high-reliability mode in a computer system 失效
标题翻译：在计算机系统中选择性使用高可靠性模式的架构支持
公开(公告)号：US20050240793A1
公开(公告)日：2005-10-27
申请号：US10819241
申请日：2004-04-06
申请人： Kevin Safford , Donald Soltis
发明人： Kevin Safford , Donald Soltis
IPC分类号： G06F9/30 , G06F11/00
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/30189 , G06F9/3851 , G06F11/1629 , G06F2201/845
摘要： In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-high-reliability mode of operation. The circuit includes means for causing the circuit to enter the high-reliability mode of operation in response to receiving the second instruction group; means for causing the circuit to enter the non-high-reliability mode of operation in response to receiving the third instruction group; first execution means for executing the first instruction group in the high-reliability mode of operation if the circuit is in the high-reliability mode of operation; and second execution means for executing the first instruction group without in the non-high-reliability mode of operation if the circuit is in the non-high-reliability mode of operation.
摘要翻译：在本发明的一个方面，提供一种电路，其实现定义第一指令组的指令集架构，进入高可靠性操作模式的第二指令组，以及进入非高速模式的第三指令组，可靠的运行模式。电路包括用于响应于接收到第二指令组而使电路进入高可靠性操作模式的装置; 响应于接收到第三指令组使电路进入非高可靠性操作模式的装置; 如果电路处于高可靠性操作模式，则在高可靠性操作模式下执行第一指令组的第一执行装置; 以及第二执行装置，用于如果电路处于非高可靠性操作模式，则在不处于非高可靠性操作模式的情况下执行第一指令组。

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