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11. 发明授权

US06734458B2 Test pattern for measuring contact resistance and method of manufacturing the same 失效
标题翻译：用于测量接触电阻的测试图案及其制造方法
公开(公告)号：US06734458B2
公开(公告)日：2004-05-11
申请号：US10029390
申请日：2001-12-28
申请人： Ki Seog Kim , Young Seon You , Keun Woo Lee , Sung Kee Park
发明人： Ki Seog Kim , Young Seon You , Keun Woo Lee , Sung Kee Park
IPC分类号： H01L2358
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a test pattern for measuring a contact resistance and method of manufacturing the same. In order to confirm that a contact resistance suitable for a semiconductor device before an actual process for manufacturing the device is performed, the present invention designs a test pattern for measuring the contact resistance depending on a design rule of a line contact actually applied to an actual device. At this time, a first line contact region and a second line contact region are formed between a word line so that a line contact region can form a pair; a plurality of sources are formed in the first line contact region and a plurality of sources are formed in the second line contact region wherein neighboring sources are connected by diffusion layers so that the first line contact region and the second line contact region can be electrically connected; and a plurality of line contact patterns are formed so that the plurality of the sources can be electrically connected by every two in each of the first and second line contact regions wherein the line contact pattern formed in the first line contact region and the line contact pattern formed in the second line contact region are alternately positioned. Therefore, the present invention can allow current for measuring the resistance sequentially along the first line contact region and the second line contact region to measure the line contact resistance in which the contact resistance in every source portion is considered.
摘要翻译：本发明涉及一种测量接触电阻的测试图案及其制造方法。为了确认在进行用于制造该器件的实际工艺之前适用于半导体器件的接触电阻，本发明根据实际应用于实际的线路接触的设计规则来设计用于测量接触电阻的测试图案设备。此时，在字线之间形成第一线接触区域和第二线路接触区域，使得线路接触区域可以形成一对; 多个源极形成在第一线路接触区域中，并且多个源极形成在第二线路接触区域中，其中相邻源极通过扩散层连接，使得第一线路接触区域和第二线路接触区域可以电连接 ; 并且形成多个线接触图案，使得多个源可以在形成在第一线接触区域中的线接触图案和线接触图案的第一和第二线路接触区域中的每一个中每两个电连接一次形成在第二线接触区域中的交替位置。因此，本发明可以允许沿着第一线路接触区域和第二线路接触区域依次测量电阻的电流来测量考虑到每个源极部分中的接触电阻的线路接触电阻。

12. 发明授权

US07099198B2 Row decoder in flash memory and erase method of flash memory cell using the same 有权
标题翻译：闪存中的行解码器和闪存单元的擦除方法使用相同
公开(公告)号：US07099198B2
公开(公告)日：2006-08-29
申请号：US10968687
申请日：2004-10-19
申请人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
发明人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C16/16 , G11C29/70
摘要： A row decoder in a flash memory comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage terminal. The row decoder also comprises a third switch to selectively couple the word line to a third voltage terminal.
摘要翻译：闪速存储器中的行解码器包括用于选择性地将字线耦合到第一电压端子的第一开关和用于选择性地将字线耦合到第二电压端子的第二开关。行解码器还包括用于选择性地将字线耦合到第三电压端子的第三开关。

13. 发明授权

US07067425B2 Method of manufacturing flash memory device 失效
标题翻译：制造闪存设备的方法
公开(公告)号：US07067425B2
公开(公告)日：2006-06-27
申请号：US10736720
申请日：2003-12-16
申请人： Keun Woo Lee
发明人： Keun Woo Lee
IPC分类号： H01L21/302
CPC分类号： H01L27/11521 , H01L21/26586 , H01L21/76237 , H01L27/115
摘要： A method of manufacturing a flash memory device includes the steps of forming a nitride film on an entire surface of a trench by means of an annealing process to prevent implanted ions for adjusting a threshold voltage from diffusing to a device isolation region, and forming a side wall oxide film on a surface of the nitride film. The nitride film plays a role of preventing ions implanted into a substrate for adjusting a threshold voltage from flowing into the side wall oxidation film.
摘要翻译：一种制造闪存器件的方法包括以下步骤：通过退火工艺在沟槽的整个表面上形成氮化物膜，以防止注入的离子调节阈值电压扩散到器件隔离区域，并形成侧面氮化膜表面上的氧化膜膜。氮化物膜起到防止植入衬底中的离子来调节阈值电压以流入侧壁氧化膜的作用。

14. 发明授权

US06819597B2 Row decoder in flash memory and erase method of flash memory cell using the same 有权
标题翻译：闪存中的行解码器和闪存单元的擦除方法使用相同
公开(公告)号：US06819597B2
公开(公告)日：2004-11-16
申请号：US10614229
申请日：2003-07-07
申请人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
发明人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
IPC分类号： G11C1606
CPC分类号： G11C16/08 , G11C16/16 , G11C29/70
摘要： Disclosed are a row decoder in a flash memory and erasing method in a flash memory cell using the same. The row decoder comprises a PMOS transistor having a gate electrode for receiving a first input signal as an input and connected between a first power supply terminal and a first node, a first NMOS transistor having a gate electrode for receiving the first input signal as an input and connected between the first node and a second node, a second NMOS transistor having a gate electrode for receiving the second input signal as an input and connected between the second node and a ground terminal, and a switching means having a gate electrode for receiving the third input signal as an input and connected between the second node and a second power supply terminal, wherein the first node is connected to word lines.
摘要翻译：本发明公开了一种闪速存储器中的行解码器和使用其的擦除方法。行解码器包括具有用于接收第一输入信号作为输入并连接在第一电源端子和第一节点之间的栅电极的PMOS晶体管，具有用于接收第一输入信号作为输入的栅电极的第一NMOS晶体管并连接在第一节点和第二节点之间的第二NMOS晶体管，具有用于接收第二输入信号作为输入并连接在第二节点和接地端子之间的栅电极的第二NMOS晶体管，以及具有栅电极的开关装置，第三输入信号作为输入并连接在第二节点和第二电源端子之间，其中第一节点连接到字线。

15. 发明授权

US06316313B1 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US06316313B1
公开(公告)日：2001-11-13
申请号：US09717002
申请日：2000-11-22
申请人： Sung Kee Park , Ki Seog Kim , Sang Hoan Chang , Keun Woo Lee
发明人： Sung Kee Park , Ki Seog Kim , Sang Hoan Chang , Keun Woo Lee
IPC分类号： H01L218247
CPC分类号： H01L27/112
摘要： There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a well resistance and a parasitic capacitance are great and the erase speed of a device is slow in case of the conventional flash memory device, the present invention forms a well region of a sector unit by use of a metal silicide layer and defines an unit cell by use of a ploysilicon layer. Thus, it can reduce the well resistance and the parasitic capacitance. Also, it can improve the operating speed of the device and can reduce the manufacturing cost by allowing the erase operation of a cell unit.
摘要翻译：公开了一种制造闪速存储器件的方法。为了解决现有的闪速存储器件的情况下阱电阻和寄生电容大的问题以及器件的擦除速度较慢的问题，本发明通过使用金属形成扇区单元的阱区硅化物层并且通过使用合金层来限定晶胞。因此，它可以降低阱电阻和寄生电容。此外，它可以提高装置的操作速度，并且可以通过允许单元单元的擦除操作来降低制造成本。

16. 发明授权

US10812425B2 Method and system for providing quiz together with advertisement in instant message service (IMS) chat room 有权
公开(公告)号：US10812425B2
公开(公告)日：2020-10-20
申请号：US16339985
申请日：2017-09-29
申请人： Chang Sub Jeon , Keun Woo Lee
发明人： Chang Sub Jeon , Keun Woo Lee , Yong Joo Shim
IPC分类号： G06F15/16 , H04L12/58 , A63F13/80 , G06Q30/02 , H04L12/18
摘要： A method, system, and quiz server for providing a quiz and an advertisement simultaneously in an IMS chat is provided. The method includes creating a chat room from a mobile terminal while inviting a pre-registered quizbot as a chat participant, displaying a quiz and an advertisement within the chat room on the mobile terminal in the form of a chat message composed by the quizbot, and displaying, within the chat room, an answer of a certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot, displaying, within the chat room, the answer of the certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot.

17. 发明授权

US07785827B2 Method and composition for leucyl-tRNA synthetases and derivatives thereof that activate and aminoacylate non-leucine amino acid to tRNA adaptor molecules 有权
标题翻译：亮氨酰tRNA合成酶及其衍生物的方法和组合物，其将非亮氨酸氨基酸活化并氨酰化至tRNA衔接子分子
公开(公告)号：US07785827B2
公开(公告)日：2010-08-31
申请号：US10251648
申请日：2002-09-20
申请人： Susan A. Martinis , James M. Briggs , Richard S. Mursinna , Keun Woo Lee , Tommie L. Lincecum , Amy M. Williams , Yuxin Zhai
发明人： Susan A. Martinis , James M. Briggs , Richard S. Mursinna , Keun Woo Lee , Tommie L. Lincecum , Amy M. Williams , Yuxin Zhai
IPC分类号： C07K14/47 , C07H21/04 , C12P21/06
CPC分类号： C12N9/93
摘要： A method and composition for tRNA synthetases that activate and aminoacylate nonstandard and noncognate amino acids to tRNA adaptor molecules is described that can be used to generate custom designed protein products for uses in medicinal, therapeutic, diagnostic, biotechnology, engineering, and spectroscopy applications. Some tRNA synthetases naturally misactivate and misaminoacylate noncognate amino acids. Many of these tRNA synthetases, including but not limited to leucyl-, isoleucyl-, and valyl-tRNA synthetases, have evolved proofreading and editing mechanisms to correct these mistakes. Inactivation of the enzyme's editing activity allows and facilitates production and accumulation of tRNAs that are misaminoacylated with nonstandard and noncognate amino acids. These misaminoacylated tRNAs can be used to introduce novel amino acids into proteins.
摘要翻译：描述了用于将非标准和非认可氨基酸激活和氨基化至tRNA衔接子分子的tRNA合成酶的方法和组合物，其可用于产生用于药物，治疗，诊断，生物技术，工程和光谱学应用的定制设计的蛋白质产物。一些tRNA合成酶天然失活和非氨基酸化非识别氨基酸。许多这些tRNA合成酶，包括但不限于亮氨酰，异亮氨酰和缬氨酰-tRNA合成酶，已经发展了校正和编辑机制，以纠正这些错误。酶的编辑活性的失活允许并促进用非标准和非认知氨基酸错氨基酰化的tRNA的产生和积累。这些错氨基酰化的tRNA可用于将新的氨基酸引入蛋白质。

18. 发明授权

US07358560B2 Flash memory device and method of manufacturing the same 失效
标题翻译：闪存装置及其制造方法
公开(公告)号：US07358560B2
公开(公告)日：2008-04-15
申请号：US11479444
申请日：2006-06-30
申请人： Keun Woo Lee
发明人： Keun Woo Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A non-volatile memory device includes a semiconductor substrate having an active region defined by isolation films that extend along a first direction. A control gate line extends along in a second direction perpendicular to the first direction. First and second floating gates are formed on the active region and below the control gate line. An island conductive line is formed between the first and second floating gates and within the isolation films. The island conductive line extends along the first direction and is configured to receive a voltage in order to prevent interference between the first and second floating gates.
摘要翻译：非易失性存储器件包括具有由沿着第一方向延伸的隔离膜限定的有源区的半导体衬底。控制栅极线沿垂直于第一方向的第二方向延伸。第一和第二浮栅形成在有源区和控制栅线下方。岛状导电线形成在第一和第二浮栅之间以及隔离膜内。岛状导电线沿着第一方向延伸并且被配置为接收电压，以便防止第一和第二浮动栅极之间的干扰。

19. 发明授权

US07358558B2 Flash memory device 有权
标题翻译：闪存设备
公开(公告)号：US07358558B2
公开(公告)日：2008-04-15
申请号：US11275273
申请日：2005-12-21
申请人： Keun Woo Lee
发明人： Keun Woo Lee
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42336 , H01L29/66825
摘要： A floating gate of a flash memory device is formed in a moat formed in an isolation film. Therefore, an electric field applied between a control gate and a channel region upon cycling can be precluded or mitigated. A distance between the control gate and the channel region is set greater than a predetermined value. Therefore, an electric field applied between the control gate and the channel region upon cycling can be mitigated. As a result, a data retention characteristic and an endurance characteristic can be improved.
摘要翻译：闪存器件的浮栅形成在隔离膜中形成的护城河。因此，可以排除或减轻在循环时在控制栅极和通道区域之间施加的电场。控制栅极和沟道区域之间的距离设定为大于预定值。因此，可以减轻在循环时在控制栅极和沟道区域之间施加的电场。结果，可以提高数据保持特性和耐久性。

20. 发明授权

US07031190B2 Structure for testing NAND flash memory and method of testing NAND flash memory 有权
标题翻译：用于测试NAND闪存的结构和测试NAND闪存的方法
公开(公告)号：US07031190B2
公开(公告)日：2006-04-18
申请号：US10737571
申请日：2003-12-16
申请人： Keun Woo Lee
发明人： Keun Woo Lee
IPC分类号： G11C16/04
CPC分类号： G11C29/50 , G11C16/04 , G11C16/0483 , G11C16/3418 , G11C16/3454 , G11C29/02 , G11C29/1201 , G11C29/50004 , G11C2029/1204 , G11C2029/5004
摘要： Provided is a structure for testing a NAND flash memory including a first string select transistor for controlling transfer of a voltage inputted via a first bit line; a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program or erase state depending on a voltage inputted thereto; a second string select transistor for controlling transfer of a voltage inputted via a second bit line; a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program or erase state depending on a voltage inputted thereto; and a measurement pad connected to a point where the first or second string select transistor and the flash memory cell are connected.
摘要翻译：提供了一种用于测试NAND闪存的结构，包括：用于控制经由第一位线输入的电压的传送的第一串选择晶体管; 连接在第一串选择晶体管和第一源选择晶体管之间的具有多个闪存单元的第一串，并且根据输入的电压保持编程或擦除状态; 第二串选择晶体管，用于控制经由第二位线输入的电压的传送; 具有连接在第二串选择晶体管和第二源极选择晶体管之间的多个闪存单元的第二串，并且根据输入的电压保持编程或擦除状态; 以及连接到第一或第二串选择晶体管和闪存单元的点连接的测量焊盘。

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