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11. 发明授权

US5151772A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5151772A
公开(公告)日：1992-09-29
申请号：US616705
申请日：1990-11-20
申请人： Yasushi Takahashi , Hiromi Matsuura , Yoshihisa Koyama , Masaya Muranaka , Katsutaka Kimura , Kazuyuki Miyazawa , Masamichi Ishihara , Hidetoshi Iwai
发明人： Yasushi Takahashi , Hiromi Matsuura , Yoshihisa Koyama , Masaya Muranaka , Katsutaka Kimura , Kazuyuki Miyazawa , Masamichi Ishihara , Hidetoshi Iwai
IPC分类号： H01L23/522 , H01L27/108
CPC分类号： H01L23/5226 , H01L27/10805 , H01L2924/0002 , Y10S257/923
摘要： A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.
摘要翻译：提供一种半导体集成电路器件，其包括位于半导体衬底的大致中心区域中的存储单元阵列，其具有位于半导体衬底两端的外围电路。还提供了将外围电路彼此耦合的布线层。该布线层被布置成具有彼此电耦合的第一和第二铝层的双层结构。

12. 发明授权

US4796234A Semiconductor memory having selectively activated blocks including CMOS sense amplifiers 失效
标题翻译：半导体存储器具有选择性地激活的块，包括CMOS读出放大器
公开(公告)号：US4796234A
公开(公告)日：1989-01-03
申请号：US927144
申请日：1986-11-05
申请人： Kiyoo Itoh , Yoshiki Kawajiri , Katsutaka Kimura , Ryoichi Hori , Jun Etoh
发明人： Kiyoo Itoh , Yoshiki Kawajiri , Katsutaka Kimura , Ryoichi Hori , Jun Etoh
IPC分类号： G11C11/409 , G11C7/06 , G11C8/12 , G11C8/14 , G11C11/401 , G11C11/4091 , G11C7/00
CPC分类号： G11C8/14 , G11C11/4091 , G11C7/06 , G11C8/12
摘要： It is contemplated to realize a semiconductor memory with a large memory capacity, high in integration and low in power dissipation. A semiconductor memory is disclosed, comprising a plurality of blocks each having a memory cell array and sense amplifier(s) to differentially amplify signals read out from the array, wherein a common driving line of amplifiers composed of N-channel MOS transistors among said sense amplifiers and a common driving line of amplifiers composed of P-channel MOS transistors among the sense amplifers are connected between different blocks.
摘要翻译：可以想到实现具有大存储容量，高集成度和低功耗的半导体存储器。公开了一种半导体存储器，包括多个块，每个块具有存储单元阵列和读出放大器，用于差分放大从阵列读出的信号，其中由所述感测中的N沟道MOS晶体管组成的公共驱动线放大器和由感测放大器中的P沟道MOS晶体管组成的放大器的公共驱动线连接在不同的块之间。

13. 发明授权

US5872734A Semiconductor nonvolatile memory device and computer system using the same 失效
标题翻译：半导体非易失性存储器件和使用其的计算机系统
公开(公告)号：US5872734A
公开(公告)日：1999-02-16
申请号：US60364
申请日：1998-04-15
申请人： Toshihiro Tanaka , Masataka Kato , Katsutaka Kimura , Tetsuya Tsujikawa , Kazuyoshi Oshima , Kazuyuki Miyazawa
发明人： Toshihiro Tanaka , Masataka Kato , Katsutaka Kimura , Tetsuya Tsujikawa , Kazuyoshi Oshima , Kazuyuki Miyazawa
IPC分类号： G11C17/00 , G11C7/10 , G11C16/06 , G11C16/26 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C7/103 , G11C16/26
摘要： A semiconductor nonvolatile memory device including transistors whose threshold voltages can be electrically rewritten (erased, written). A read-selected word line voltage Vrw, lower than the supply voltage Vcc applied from the outside, is applied, and the threshold voltage difference between the higher threshold voltage VthH and the lower threshold voltage VthL in the two states of nonvolatile memory cells is reduced to bring the higher threshold voltage VthH close to the lower threshold voltage VthL. Moreover, a threshold voltage Vthi in the thermally equilibrium state of the memory cell, corresponding to the two threshold voltages of the two states, is set between the higher threshold voltage VthH and the lower threshold voltage VthL.
摘要翻译：一种包括晶体管的半导体非易失性存储器件，其阈值电压可被电刷写（擦除，写入）。施加低于从外部施加的电源电压Vcc的读取选择字线电压Vrw，并且在非易失性存储单元的两种状态下的较高阈值电压VthH与较低阈值电压VthL之间的阈值电压差减小以使较高的阈值电压VthH接近于较低的阈值电压VthL。此外，与两个状态的两个阈值电压对应的存储单元的热平衡状态下的阈值电压Vthi设定在较高阈值电压VthH与下限阈值电压VthL之间。

14. 发明授权

US5748532A Semiconductor nonvolatile memory device and computer system using the same 失效
标题翻译：半导体非易失性存储器件和使用其的计算机系统
公开(公告)号：US5748532A
公开(公告)日：1998-05-05
申请号：US677842
申请日：1996-07-10
申请人： Toshihiro Tanaka , Masataka Kato , Katsutaka Kimura , Tetsuya Tsujikawa , Kazuyoshi Oshima , Kazuyuki Miyazawa
发明人： Toshihiro Tanaka , Masataka Kato , Katsutaka Kimura , Tetsuya Tsujikawa , Kazuyoshi Oshima , Kazuyuki Miyazawa
IPC分类号： G11C17/00 , G11C7/10 , G11C16/06 , G11C16/26 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C7/103 , G11C16/26
摘要： A semiconductor nonvolatile memory device including transistors whose threshold voltages can be electrically rewritten (erased, written). A read-selected word line voltage Vrw, lower than the supply voltage Vcc applied from the outside, is applied, and the threshold voltage difference between the higher threshold voltage VthH and the lower threshold voltage VthL in the two states of the nonvolatile memory cells is reduced to bring the higher threshold voltage VthH close to the lower threshold voltage VthL. Moreover, a threshold voltage Vthi in the thermally equilibrium state of the memory cell, corresponding to the two threshold voltages of the two states, is set between the higher threshold voltage VthH and the lower threshold voltage VthL.
摘要翻译：一种包括晶体管的半导体非易失性存储器件，其阈值电压可被电刷写（擦除，写入）。施加低于从外部施加的电源电压Vcc的读取选择的字线电压Vrw，并且非易失性存储单元的两种状态下的较高阈值电压VthH与较低阈值电压VthL之间的阈值电压差为减小以使较高的阈值电压VthH接近于较低的阈值电压VthL。此外，与两个状态的两个阈值电压对应的存储单元的热平衡状态下的阈值电压Vthi设定在较高阈值电压VthH与下限阈值电压VthL之间。

15. 发明授权

US4916700A Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US4916700A
公开(公告)日：1990-04-10
申请号：US156897
申请日：1988-02-17
申请人： Kazuya Ito , Katsutaka Kimura , Kazuyuki Miyazawa
发明人： Kazuya Ito , Katsutaka Kimura , Kazuyuki Miyazawa
IPC分类号： G11C29/00 , G11C11/401 , G11C29/34
CPC分类号： G11C29/34
摘要： A semiconductor storage device is disclosed which has a plurality of common data lines for delivering information from plural memory cells selected out of a plurality of memory cells during a normal operation mode, a plurality of amplifier circuits provided corresponding to the plurality of common data lines, a plurality of first testing logical circuits each one of which is provided for plural amplifier circuits which are disposed in close vicinity to each other of the plurality of amplifier circuits, and a second testing logical circuit for receiving each of output signals from the plurality of first testing logical circuits during the testing mode.
摘要翻译：公开了一种半导体存储装置，其具有多个公共数据线，用于在正常操作模式期间从多个存储单元中选择的多个存储单元传送信息;对应于多个公共数据线提供的多个放大器电路，多个第一测试逻辑电路，每个第一测试逻辑电路被设置用于多个放大器电路中的多个放大器电路，所述多个放大器电路被布置在所述多个放大器电路中彼此相邻;以及第二测试逻辑电路，用于接收来自所述多个第一在测试模式下测试逻辑电路。

16. 发明申请

US20110051515A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20110051515A1
公开(公告)日：2011-03-03
申请号：US12791177
申请日：2010-06-01
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.
摘要翻译：公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中的非易失性存储单元。此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

17. 发明申请

US20070297257A1 Semiconductor memory device capable of canceling out noise development 审中-公开
标题翻译：能够消除噪声发展的半导体存储器件
公开(公告)号：US20070297257A1
公开(公告)日：2007-12-27
申请号：US11889902
申请日：2007-08-17
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor and a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.
摘要翻译：动态RAM包含多个动态存储单元，每个动态存储单元包括具有作为选择端子的栅极集合的MOSFET，作为输入/输出端子的一个源极和漏极组，以及连接到电容器的存储节点的另一个源极和漏极以及电容器，分别连接到多个动态存储单元的选择端子的多个字线，分别连接到多个动态存储单元的输入/输出端子的多个互补位线对，以及读出放大器阵列包括多个锁存电路，其分别放大互补位线对之间的电压差，以便从每对输入/输出端子彼此相反的方向延伸。电源线以网格形式提供，包括字驱动器上方的一部分。

18. 发明申请

US20070195596A1 Semiconductor integrated circuit device, production and operation method thereof 有权
标题翻译：半导体集成电路器件，其生产和操作方法
公开(公告)号：US20070195596A1
公开(公告)日：2007-08-23
申请号：US11700085
申请日：2007-01-31
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0425 , G11C16/12 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.
摘要翻译：一种半导体集成器件，具有多个存储单元，每个存储单元包括通过绝缘膜形成在浮置栅极的侧表面上的浮置栅极，控制栅极和辅助栅极。耦合到选择的存储单元的辅助栅极用于产生热电子，并且与其他辅助栅极交替布置，其功能是防止未选择的存储器单元中的写入错误。

19. 发明申请

US20060039218A1 Semiconductor device 失效
公开(公告)号：US20060039218A1
公开(公告)日：2006-02-23
申请号：US11206016
申请日：2005-08-18
申请人： Riichiro Takemura , Kiyoo Itoh , Tomonori Sekiguchi , Takeshi Sakata , Katsutaka Kimura
发明人： Riichiro Takemura , Kiyoo Itoh , Tomonori Sekiguchi , Takeshi Sakata , Katsutaka Kimura
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C5/025 , G11C5/14 , G11C7/06 , G11C7/08 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C2207/065 , H01L27/0207 , H01L27/10894
摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.

20. 发明授权

US06944080B2 Dynamic random access memory(DRAM) capable of canceling out complimentary noise developed in plate electrodes of memory cell capacitors 有权
标题翻译：动态随机存取存储器（DRAM）能够消除在存储单元电容器的平板电极中产生的互补噪声
公开(公告)号：US06944080B2
公开(公告)日：2005-09-13
申请号：US10938794
申请日：2004-09-13
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C7/02 , G11C7/18 , G11C8/00 , G11C11/34 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring using the common electrodes.
摘要翻译：一种动态RAM，包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到所述多个动态存储单元的输入/输出端的多个互补位线对，并且被放置在与以及根据操作定时信号提供工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。在动态RAM中，与以感测放大器阵列为中心的两侧的多个动态存储单元的地址选择MOSFET和信息存储电容器之间的连接点对应的存储节点提供的公共电极彼此连接而通过使用公共电极的布线来确保读出放大器阵列中的电路连接。

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