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11. 发明授权

US07785965B2 Dual storage node memory devices and methods for fabricating the same 有权
标题翻译：双存储节点存储器件及其制造方法
公开(公告)号：US07785965B2
公开(公告)日：2010-08-31
申请号：US11530145
申请日：2006-09-08
申请人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
发明人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/7923
摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.
摘要翻译：已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。层状结构包括隧道介电层和电荷存储层。位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

12. 发明授权

US07759745B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07759745B2
公开(公告)日：2010-07-20
申请号：US11656437
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/10 , H01L29/739
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并在其上掺杂有杂质的重掺杂深杂质区域（7b）浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的改善。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

13. 发明授权

US07683440B2 Semiconductor memory device 有权
公开(公告)号：US07683440B2
公开(公告)日：2010-03-23
申请号：US11656437
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/10 , H01L29/739
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

14. 发明授权

US07635627B2 Methods for fabricating a memory device including a dual bit memory cell 有权
标题翻译：一种用于制造包括双位存储单元的存储器件的方法
公开(公告)号：US07635627B2
公开(公告)日：2009-12-22
申请号：US11614050
申请日：2006-12-20
申请人： Ning Cheng , Hiroyuki Kinoshita , Minghao Shen , Ashot Melik-Martirosian
发明人： Ning Cheng , Hiroyuki Kinoshita , Minghao Shen , Ashot Melik-Martirosian
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792
摘要： Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.
摘要翻译：提供了用于制造包括双位存储单元的存储器件的方法。该方法包括根据本发明的一个实施例，在半导体衬底的表面上形成覆盖栅极电介质层的栅极电介质层和中心栅电极。第一和第二存储器存储节点形成在栅极电介质层的侧面附近，第一和第二存储节点中的每一个包括第一介电层和电荷存储层，第一电介质层独立于形成栅极电介质的步骤而形成层。第一控制栅极形成在第一存储器存储节点上，并且第二控制栅极形成在第二存储器存储节点上。导电层被沉积并图案化以形成耦合到中央栅电极，第一控制栅极和第二控制栅极的字线。

15. 发明申请

US20090295079A1 SHEET CONVEYING APPARATUS AND IMAGE FORMING APPARATUS 有权
标题翻译：输送装置和图像形成装置
公开(公告)号：US20090295079A1
公开(公告)日：2009-12-03
申请号：US12465977
申请日：2009-05-14
申请人： Hiroyuki Kinoshita , Hideyuki Terashima , Naohiro Iwata , Kosuke Yamamoto , Akihiro Tomoda , Ryosuke Sato , Akio Okubo
发明人： Hiroyuki Kinoshita , Hideyuki Terashima , Naohiro Iwata , Kosuke Yamamoto , Akihiro Tomoda , Ryosuke Sato , Akio Okubo
IPC分类号： B65H9/00
CPC分类号： B65H9/006 , B65H2403/70 , B65H2404/1424 , B65H2404/1531 , B65H2405/332
摘要： A first conveying mechanism includes an intermediate conveying roller for conveying a recording sheet, an intermediate conveying roller shaft for supporting the intermediate conveying roller, an intermediate conveying roller drive mechanism for rotationally driving the intermediate conveying roller shaft, and a roller control mechanism for controlling movements of the intermediate conveying roller relative to the intermediate conveying roller shaft. The roller control mechanism performs skew correction along with conveying the recording sheet by rotating the intermediate conveying roller integrally with the intermediate conveying roller shaft while the intermediate conveying roller drive mechanism rotationally drives the intermediate conveying roller shaft and stops the rotational drive of the intermediate conveying roller shaft performed by the intermediate conveying roller drive mechanism after the skew correction to cause the intermediate conveying roller to be movable within a predetermined range in the axial direction of the intermediate conveying roller shaft.
摘要翻译：第一输送机构包括用于输送记录纸的中间输送辊，用于支撑中间输送辊的中间输送辊轴，用于旋转驱动中间输送辊轴的中间输送辊驱动机构，以及用于控制运动的辊控制机构中间输送辊相对于中间输送辊轴。当中间输送辊驱动机构旋转地驱动中间输送辊轴并停止中间输送辊的旋转驱动时，滚子控制机构通过与中间输送辊轴一体地旋转中间输送辊而进行扭曲校正以及输送记录纸在偏斜校正之后由中间输送辊驱动机构执行的轴，以使中间输送辊能够在中间输送辊轴的轴向方向上的预定范围内移动。

16. 发明申请

US20090278902A1 PRINTER 有权
标题翻译：打印机
公开(公告)号：US20090278902A1
公开(公告)日：2009-11-12
申请号：US12430435
申请日：2009-04-27
申请人： Naohiro Iwata , Hiroyuki Kinoshita , Hideyuki Terashima , Akihiro Tomoda , Ryosuke Sato , Kosuke Yamamoto
发明人： Naohiro Iwata , Hiroyuki Kinoshita , Hideyuki Terashima , Akihiro Tomoda , Ryosuke Sato , Kosuke Yamamoto
IPC分类号： B41J2/175
CPC分类号： B41J2/1752 , B41J25/34
摘要： A printer includes a set cover pivotally movably provided on a carriage. The cover can be set in a closed state in which the cover presses a head of the cartridge housed in the housing portion and an open state in which the cover opens the housing portion when the cartridge is replaced. A release lever is subjected to a bias force so as to protrude from an inner wall surface of the housing portion. The release lever is movable against the bias force. The release lever comes into contact with an end of the cartridge which faces the bottom surface when the cartridge is inserted into the housing portion. The release lever contacts the rear surface of the cartridge housed in the housing portion. The bias force is stronger when the cover is in the open state than when the cover is in the closed state.
摘要翻译：打印机包括可枢转地可移动地设置在托架上的套盖。盖可以设置在关闭状态，其中盖压住容纳在壳体部分中的盒的头部，并且当盒更换时盖打开壳体部分的打开状态。释放杆受到偏压力，从而从壳体部分的内壁表面突出。释放杆可抵抗偏压力移动。当盒被插入到壳体部分中时，释放杆与盒的面向底表面的端部接触。释放杆接触容纳在壳体部分中的盒的后表面。当盖处于打开状态时，当盖处于关闭状态时，偏压力更强。

17. 发明申请

US20090096819A1 DRIVING CIRCUIT APPARATUS 审中-公开
标题翻译：驱动电路设备
公开(公告)号：US20090096819A1
公开(公告)日：2009-04-16
申请号：US12237604
申请日：2008-09-25
申请人： Hiroyuki Kinoshita
发明人： Hiroyuki Kinoshita
IPC分类号： G09G5/02 , G09G5/10
CPC分类号： G09G3/3685 , G09G3/3696 , G09G2320/0276 , G09G2320/0285
摘要： A driving circuit that reduces chip size of a source driver while maintaining image quality when image data is configured by multiple bits. The source driver provided in connection with a timing controller that converts image data into color data. The source driver displays an image by controlling pixel density of a liquid crystal panel. The source driver is divided into plural regions in units of pseudo linear elements to perform a gamma correcting operation based on a gamma characteristic. In the source driver a GMA voltage for each region is divided by resistive elements arranged between input signal lines. With respect to variation of plural divided GMA voltages, variation of the maximum high density region becomes coarser than variation of the maximum low density region in compliance with visual sensitivity of the density, thus reducing the number of input data lines of the source driver.
摘要翻译：驱动电路，当图像数据由多位配置时，可以在保持图像质量的同时降低源驱动器的芯片尺寸。提供的源驱动程序与将图像数据转换为彩色数据的定时控制器相关联。源驱动器通过控制液晶面板的像素密度来显示图像。源极驱动器以伪线性元件为单位分成多个区域，以基于伽马特性进行伽马校正操作。在源极驱动器中，每个区域的GMA电压由布置在输入信号线之间的电阻元件分压。对于多个分割的GMA电压的变化，最大高密度区域的变化比密度的视觉灵敏度的最大低密度区域的变化更粗糙，因此减少了源极驱动器的输入数据线的数量。

18. 发明授权

US07482226B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07482226B2
公开(公告)日：2009-01-27
申请号：US11656438
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并在其上掺杂有杂质的重掺杂深杂质区域（7b）浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的改善。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

19. 发明申请

US20080315290A1 MEMORY DEVICE AND METHODS FOR ITS FABRICATION 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20080315290A1
公开(公告)日：2008-12-25
申请号：US12199692
申请日：2008-08-27
申请人： Chungho LEE , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
发明人： Chungho LEE , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
IPC分类号： H01L29/00
CPC分类号： H01L21/28282 , H01L29/42332 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.
摘要翻译：提供半导体存储器件及其制造方法。根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

20. 发明申请

US20080149988A1 SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20080149988A1
公开(公告)日：2008-06-26
申请号：US11615365
申请日：2006-12-22
申请人： Hiroyuki Kinoshita , Ning Cheng , Minghao Shen
发明人： Hiroyuki Kinoshita , Ning Cheng , Minghao Shen
IPC分类号： H01L29/423 , H01L21/71
CPC分类号： H01L27/11563 , H01L27/115 , H01L27/11568
摘要： Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon.
摘要翻译：提供了用于制造存储器件的方法。一种方法包括制造覆盖在硅衬底上的电荷俘获堆叠，并在电荷俘获堆叠之间形成衬底中的位线区域。绝缘元件形成在堆叠之间的位线区域之上。电荷俘获堆被蚀刻以形成两个互补电荷存储节点并暴露硅衬底的部分。硅通过选择性外延生长在暴露的硅衬底上生长并被氧化。形成覆盖互补电荷存储节点和氧化的外延生长硅的控制栅层。

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