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11. 发明授权

US5231138A Thermoplastic and elastomeric composition comprising a polyamide and a rubber component 失效
标题翻译：包含聚酰胺和橡胶组分的热塑性弹性体组合物
公开(公告)号：US5231138A
公开(公告)日：1993-07-27
申请号：US639438
申请日：1991-01-10
申请人： Mitsuyoshi Aonuma , Tatsunosuke Suzuki , Satoru Isomura , Koichi Nishimura
发明人： Mitsuyoshi Aonuma , Tatsunosuke Suzuki , Satoru Isomura , Koichi Nishimura
IPC分类号： C08L77/00
CPC分类号： C08L77/00
摘要： A thermoplastic and elastomeric composition comprising a polyamide resin and a rubber component, wherein the rubber component is dispersed in the form of crosslinked particles in the polyamide resin.
摘要翻译：一种包含聚酰胺树脂和橡胶组分的热塑性弹性体组合物，其中橡胶组分以聚酰胺树脂中交联颗粒的形式分散。

12. 发明授权

US4996264A Thermoplastic and elastomeric composition 失效
标题翻译：热塑性和弹性体组成
公开(公告)号：US4996264A
公开(公告)日：1991-02-26
申请号：US235863
申请日：1988-08-23
申请人： Mitsuyoshi Aonuma , Tatsunosuke Suzuki , Satoru Isomura , Koichi Nishimura
发明人： Mitsuyoshi Aonuma , Tatsunosuke Suzuki , Satoru Isomura , Koichi Nishimura
IPC分类号： C08L9/02 , C08L21/00 , C08L33/04 , C08L33/06 , C08L33/08 , C08L77/00
CPC分类号： C08L77/00
摘要： A thermoplastic and elastomeric composition comprising a polyamide resin and a rubber component, wherein the rubber component is dispersed in the form of crosslinked particles in the polyamide resin.
摘要翻译：一种包含聚酰胺树脂和橡胶组分的热塑性弹性体组合物，其中橡胶组分以聚酰胺树脂中交联颗粒的形式分散。

13. 发明授权

US06937068B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06937068B2
公开(公告)日：2005-08-30
申请号：US10642138
申请日：2003-08-18
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01L27/092 , H01L27/11 , H01L27/04
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.
摘要翻译：具有CMOS电路的集成电路，其通过将n型阱2（其中CMOS电路的p沟道晶体管Tp被置位）与通过开关晶体管Tps的电源线Vdd电连接而构成，并且电连接p型阱如图3所示，其中CMOS电路的n沟道晶体管Tn被设置，电源线Vss通过开关晶体管Tns。当集成电路被测试时，可以通过关断开关晶体管Tps和Tns并从外部单元向n型阱2和p型阱3提供适合于测试的电位来控制由于泄漏电流引起的热失控。通过接通开关晶体管Tps和Tns并分别将n型阱2和p型阱3分别设置为电压Vdd和Vss可以防止闩锁现象和操作速度的波动。

14. 发明授权

US06911734B2 Semiconductor device and electronic device 失效
公开(公告)号：US06911734B2
公开(公告)日：2005-06-28
申请号：US10391746
申请日：2003-03-20
申请人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
发明人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
IPC分类号： H01L23/66 , H05K1/02 , H05K3/36 , H01L23/34
CPC分类号： H05K1/0243 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/32188 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/09701 , H01L2924/15173 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/1903 , H01L2924/19106 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/361 , H05K2201/10522 , H05K2201/1053 , H05K2201/10659 , H05K2201/10681 , H05K2201/10734 , H01L2924/00014 , H01L2924/00
摘要： A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.

15. 发明授权

US06760895B2 Design method of semiconductor device 有权
标题翻译：半导体器件的设计方法
公开(公告)号：US06760895B2
公开(公告)日：2004-07-06
申请号：US10147991
申请日：2002-05-20
申请人： Yuko Ito , Satoru Isomura
发明人： Yuko Ito , Satoru Isomura
IPC分类号： G06F945
CPC分类号： G06F17/5077 , G06F17/5036
摘要： A semiconductor device design method useful for the design of microprocessor, ASIC, and high-speed high-performance LSI is intended to enhance the accuracy of delay calculation and crosstalk noise calculation, and enhance the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk. The method calculates the delay by using the total capacitance in consideration of the actual load after the layout and wiring, carries out the layout, wiring and modification of wiring repeatedly until targeted in-cycle transfer becomes attainable, calculates the delay by using the total capacitance in consideration of the actual load and crosstalk, carries out the modification of wiring repeatedly until targeted in-cycle transfer becomes attainable, calculates the crosstalk noise by using the total capacitance and coupling capacitance in consideration of the actual load, carries out the modification of wiring repeatedly until malfunctioning subsides, and uses data after the final layout and wiring for mask data.
摘要翻译：用于微处理器，ASIC和高速高性能LSI设计的半导体器件设计方法旨在提高延迟计算和串扰噪声计算的精度，并提高串扰和检查引起的延迟变化评估的准确性由串扰引起的故障。该方法通过考虑布线和布线后的实际负载，使用总电容来计算延迟，重复布线，布线和修改布线，直到目标周期内传输达到目标，通过使用总电容计算延迟考虑到实际负载和串扰，反复进行布线修改，直到目标周期内传输成为可能，考虑到实际负载，通过使用总电容和耦合电容来计算串扰噪声，执行布线改造重复直到故障消除，并在最终布局和掩模数据接线后使用数据。

16. 发明授权

US5898636A Semiconductor integrated circuit device with interleaved memory and logic blocks 失效
标题翻译：具有交错存储器和逻辑块的半导体集成电路器件
公开(公告)号：US5898636A
公开(公告)日：1999-04-27
申请号：US255240
申请日：1994-06-07
申请人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
发明人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
IPC分类号： G11C5/02 , H01L27/02 , H03K19/177 , H01L21/82
CPC分类号： H03K19/1776 , G11C5/025 , H01L27/0207 , H03K19/1774 , H03K19/17792 , H03K19/17796
摘要： A semiconductor integrated circuit device having a memory portion and a logic circuit portion formed with a same semiconductor substrate comprising a first logic circuit block, a second logic circuit block disposed in an area different from an area in which the first logic circuit block is disposed, and a pair of memory blocks oppositely disposed so that the second logic circuit block comes in between. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit provided on the second logic circuit block. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block.
摘要翻译：一种半导体集成电路器件，具有存储部分和形成有相同半导体衬底的逻辑电路部分，该半导体衬底包括第一逻辑电路块，布置在与设置第一逻辑电路块的区域不同的区域中的第二逻辑电路块，以及相对设置的一对存储器块，使得第二逻辑电路块在其间。存储在一对存储器块中的数据被发送到第二逻辑电路块，用于经由设置在第二逻辑电路块上的存储器外围电路进行处理。经由第二逻辑电路块中提供的输入/输出电路将数据处理的结果发送到第一逻辑电路块或外部设备。

17. 发明授权

US5341049A Integrated circuit having alternate rows of logic cells and I/O cells 失效
标题翻译：集成电路具有交替行的逻辑单元和I / O单元
公开(公告)号：US5341049A
公开(公告)日：1994-08-23
申请号：US916430
申请日：1992-07-21
申请人： Atsushi Shimizu , Satoru Isomura , Takeo Yamada , Tohru Kobayashi , Yoshuhiro Fujimura , Yuko Ito
发明人： Atsushi Shimizu , Satoru Isomura , Takeo Yamada , Tohru Kobayashi , Yoshuhiro Fujimura , Yuko Ito
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1735 , H01L27/118 , H01L2224/11
摘要： A semiconductor IC device has an input/output circuit and an internal logic circuit connected with the input/output circuit formed in a main surface of a semiconductor substrate of a generally rectangular shape. The input/output circuit is divided into at least two input/output circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in a direction substantially parallel with a pair of opposite sides of the substrate. The internal logic circuit is divided into at least three logic circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in the above-mentioned direction. Each of the input/output circuit blocks is sandwiched by and electrically connected with adjacently arranged two of the logic circuit blocks.
摘要翻译：半导体IC器件具有与形成在大致矩形形状的半导体衬底的主表面中的输入/输出电路连接的输入/输出电路和内部逻辑电路。输入/输出电路被划分为至少两个输入/输出电路块，使得由基板的主表面上的划分限定的逻辑电路块的边缘沿着与一对相对侧基本平行的方向延伸的基底。内部逻辑电路被分成至少三个逻辑电路块，使得由衬底的主表面上的划分限定的逻辑电路块的边缘沿上述方向延伸。每个输入/输出电路块被夹在相邻布置的两个逻辑电路块中并与其电连接。

18. 发明授权

US07216269B2 Signal transmit-receive device, circuit, and loopback test method 失效
标题翻译：信号发射接收设备，电路和环回测试方法
公开(公告)号：US07216269B2
公开(公告)日：2007-05-08
申请号：US10309886
申请日：2002-12-05
申请人： Takashige Baba , Tatsuya Saito , Hiroki Yamashita , Yusuke Takeuchi , Satoru Isomura
发明人： Takashige Baba , Tatsuya Saito , Hiroki Yamashita , Yusuke Takeuchi , Satoru Isomura
IPC分类号： G01R31/28
CPC分类号： H04B10/035 , H04B10/071 , H04L1/243
摘要： A signal transmit-receive device of the invention reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group, and for running a loopback test on a signal transmit-receive device. The loopback test circuit uses an error detecting circuit, a test signal producing circuit, and a wiring for transmitting error information. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern. The test signal producing circuit produces the test signal pattern based on error information. If an error is detected, the error signal is transmitted to the test signal producing circuit through the wiring. The test signal producing circuit produces a predetermined test signal pattern if the error signal DE has an L level; upon receiving H level, it sends back the predetermined test signal pattern to the first communication device.
摘要翻译：本发明的信号发送接收装置减少了连接发送电路组和接收电路组所需的高速信号线的数量，并且对信号发送接收装置进行环回测试。环回测试电路使用错误检测电路，测试信号产生电路和用于发送错误信息的布线。误差检测电路将预先由第一通信设备定义的测试信号模式与接收到的信号模式进行比较。测试信号产生电路基于错误信息产生测试信号模式。如果检测到错误，则误差信号通过布线传输到测试信号产生电路。如果误差信号DE具有L电平，则测试信号产生电路产生预定的测试信号模式; 在接收到H电平后，将预定的测试信号模式发送回第一通信设备。

19. 发明授权

US6034912A Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US6034912A
公开(公告)日：2000-03-07
申请号：US145076
申请日：1998-09-01
申请人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
发明人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
IPC分类号： G11C5/02 , H01L27/02 , H03K19/177
CPC分类号： H03K19/1776 , G11C5/025 , H01L27/0207 , H03K19/1774 , H03K19/17792 , H03K19/17796
摘要： A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits. Next, the clock signal is supplied to a plurality of third state clock distributing circuits equidistantly disposed from each of the second stage clock distributing circuits and then supplied to a plurality of final stage clock distributing circuits equidistantly disposed from each of the third stage clock distributing circuits. From these final stage clock distributing circuits, the clock signal is supplied to an area in whose units an internal gate array and a RAM macro cell or a logic macro cell are made replaceable with each other.
摘要翻译：半导体器件的存储部分和逻辑电路部分形成在单个半导体衬底上，其中第一逻辑电路块和第二逻辑电路块形成在不同的区域中，并且第二逻辑电路位于一对存储块之间。存储在一对存储器块中的数据被发送到第二逻辑电路块，以经由存储器外围电路进行处理。经由第二逻辑电路块中提供的输入/输出电路将数据处理的结果发送到第一逻辑电路块或外部设备。输入到半导体芯片的中心部分的时钟信号被提供给从中心部分等距设置的多个第一状态时钟分配电路，然后被提供给至少等距地从第一状态中的每个状态设置的多个第二级时钟分配电路时钟分配电路。接下来，时钟信号被提供给从每个第二级时钟分配电路等距离设置的多个第三状态时钟分配电路，然后提供给从每个第三级时钟分配电路等距设置的多个最后级时钟分配电路。从这些最终级时钟分配电路，将时钟信号提供给其单位内的内部门阵列和RAM宏小区或逻辑宏小区彼此可替换的区域。

20. 发明授权

US5396198A Electronic circuit device having a series connection of resistor and capacitance as a noise reducing circuit connected to a power source wiring 失效
标题翻译：具有连接到电源布线的降噪电路的电阻和电容的串联连接的电子电路装置
公开(公告)号：US5396198A
公开(公告)日：1995-03-07
申请号：US118178
申请日：1993-09-09
申请人： Hiroki Yamashita , Hiroyuki Itoh , Keiichirou Nakanishi , Tatsuya Saitoh , Tohru Kobayashi , Satoru Isomura
发明人： Hiroki Yamashita , Hiroyuki Itoh , Keiichirou Nakanishi , Tatsuya Saitoh , Tohru Kobayashi , Satoru Isomura
IPC分类号： H01L23/528 , H01L23/66 , H01P5/12 , H01P1/26
CPC分类号： H01L23/5286 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H01L2924/3011
摘要： A power source wiring supplies power to individual electronic circuits constituting an electronic circuit device. Load circuits are connected to the power source wiring within the range of an arrival time of a voltage noise occurring in the power source wiring in a time of about a half of a pulse width of a noise current at the time of the operation of the electronic circuit. Each of these load circuits includes a series circuit of a resistance and a capacitance.
摘要翻译：电源线为构成电子电路装置的各电子线路供电。负载电路在电子线路中发生的电压噪声的到达时间的范围内连接到电源布线，时间为电子操作时的噪声电流的脉冲宽度的大约一半电路。这些负载电路中的每一个都包括电阻和电容的串联电路。

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