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11. 发明授权

US4262263A Variable equalizer 失效
标题翻译：可变均衡器
公开(公告)号：US4262263A
公开(公告)日：1981-04-14
申请号：US036973
申请日：1979-05-08
申请人： Yoshitaka Takasaki
发明人： Yoshitaka Takasaki
IPC分类号： H03H7/01 , H04B3/14 , H03F3/04 , H03H5/00
CPC分类号： H04B3/14 , H04B3/145
摘要： A variable equalizer for compensating for the frequency characteristics of transmission media, comprising a plurality of variable circuits which are connected in cascade to an input terminal and which have the same variation characteristics, coefficient circuits which receive input and output signals of the variable circuits as inputs thereof and which multiply the inputs by coefficients, a plurality of impedance circuits which receive as inputs thereof signals with outputs of the coefficient circuits selectively combined and which have frequency-dependencies, and an adder circuit which adds outputs of the impedance circuits to provide an equalized signal as its output. No feedback circuit is required in the construction, and the plurality of variable circuits are constructed of the same circuits. Therefore, a variable equalizer which is capable of high-speed operation, whose circuit arrangement is simple and whose compensation accuracy is high is realized.
摘要翻译：一种用于补偿传输介质的频率特性的可变均衡器，包括串联连接到输入端并具有相同变化特性的多个可变电路，接收可变电路的输入和输出信号作为输入的系数电路并且将输入乘以系数，多个阻抗电路，其接收有选择地组合并且具有频率依赖性的系数电路的输出作为其输入的信号;以及加法器电路，其将所述阻抗电路的输出相加以提供均衡的信号作为其输出。该结构中不需要反馈电路，并且多个可变电路由相同的电路构成。因此，实现了能够高速运行的可变均衡器，其电路布置简单并且其补偿精度高。

12. 发明授权

US4122417A Variable equalizer 失效
标题翻译：可变均衡器
公开(公告)号：US4122417A
公开(公告)日：1978-10-24
申请号：US796539
申请日：1977-05-13
申请人： Yoshitaka Takasaki , Kohei Ishizuka , Yasuhiro Kita , Yoshinori Nagoya , Takeo Kusama
发明人： Yoshitaka Takasaki , Kohei Ishizuka , Yasuhiro Kita , Yoshinori Nagoya , Takeo Kusama
IPC分类号： H03H7/01 , H03H11/04 , H04B3/14 , H03H7/14
CPC分类号： H04B3/145
摘要： To form a simple and economical variable equalizer, the equalizer is constructed of a differential amplifier having two input terminals to which an input signal to be equalized and an equalized output signal derived from the output terminal are applied, a first impedance circuit connected between the differential amplifier and the output terminal, and a series circuit having a second impedance circuit and a variable resistor connected in series between the output terminal and a ground terminal.
摘要翻译：为了形成简单而经济的可变均衡器，均衡器由具有两个输入端的差分放大器构成，输入端被均衡，输入信号得到均衡的输出信号，第一阻抗电路连接在差分放大器和输出端子，以及具有在输出端子和接地端子之间串联连接的第二阻抗电路和可变电阻器的串联电路。

13. 发明授权

US4097824A Variable equalizer 失效
标题翻译：可变均衡器
公开(公告)号：US4097824A
公开(公告)日：1978-06-27
申请号：US772677
申请日：1977-02-28
申请人： Kohei Ishizuka , Yasuhiro Kita , Yoshitaka Takasaki , Junichi Nakagawa
发明人： Kohei Ishizuka , Yasuhiro Kita , Yoshitaka Takasaki , Junichi Nakagawa
IPC分类号： H03H7/01 , H03H11/04 , H04B3/14 , H03H7/14
CPC分类号： H04B3/14 , H04B3/145
摘要： A variable equalizer adapted to be fabricated in an integrated circuit structure and having improved compensation characteristics comprises a parallel connection of two circuits, one including a series connection of a first impedance circuit (impedance: Zy) and an input A.C. signal source circuit having a voltage v.sub.i, the other comprising a series connection of a second impedance circuit (impedance: Z.sub.x) and an A.C. signal source circuit having a voltage amplitude v.sub.z which is equal to v.sub.i (K/Z.sub.y).sup.2, where K is a constant, and the second impedance circuit, consists of a variable resistor.
摘要翻译：适于以集成电路结构制造并具有改进的补偿特性的可变均衡器包括两个电路的并联连接，一个包括第一阻抗电路（阻抗：Zy）的串联连接和具有电压的输入AC信号源电路 vi，另一个包括第二阻抗电路（阻抗：Zx）和具有等于vi（K / Zy）2的电压幅度vz的AC信号源电路的串联连接，其中K是常数，第二阻抗电路由可变电阻组成。

14. 发明授权

US5815502A Information transmission system with variable transmission rate 失效
公开(公告)号：US5815502A
公开(公告)日：1998-09-29
申请号：US581966
申请日：1996-01-02
申请人： Atsushi Saito , Yoshitaka Takasaki , Taizo Kinoshita , Shigeki Kitajima
发明人： Atsushi Saito , Yoshitaka Takasaki , Taizo Kinoshita , Shigeki Kitajima
IPC分类号： G06F13/00 , H04L12/801 , H04L12/811 , H04L12/911 , H04L29/06 , H04L29/08 , H04M11/08 , H04N7/50 , H04N7/56 , H04N21/21 , H04N21/23 , H04N21/6377 , H04N21/658 , H04Q11/04 , H04J3/22
CPC分类号： H04L47/25 , H04L12/54 , H04L47/10 , H04L49/90 , H04L49/9047 , H04M11/08 , H04N19/115 , H04N19/152 , H04N19/164 , H04N19/184 , H04N19/61 , H04N21/21 , H04N21/23 , H04N21/6377 , H04N21/658 , H04N7/56 , H04Q11/04 , H04N19/146 , H04N19/50
摘要： A method and system for information processing in a bidirectional information transmission system, particularly for transmitting information in accordance with a change in a transmission capacity of a transmission line. A system is provided which can change an information transmission rate in accordance with a room capacity of a transmission line. This information transmission system includes a plurality of information providers, a plurality of information receivers, an information storage and distribution unit connected to the information providers and receivers, and a plurality of information transmission lines for information transmission between the information providers and receivers and the information storage and distribution unit, wherein the information transmission rate of each information transmission line is changed.

15. 发明授权

US5515368A Information transmission system with variable transmission rate 失效
标题翻译：具有可变传输速率的信息传输系统
公开(公告)号：US5515368A
公开(公告)日：1996-05-07
申请号：US226301
申请日：1994-04-12
申请人： Atsushi Saito , Yoshitaka Takasaki , Taizo Kinoshita , Shigeki Kitajima
发明人： Atsushi Saito , Yoshitaka Takasaki , Taizo Kinoshita , Shigeki Kitajima
IPC分类号： G06F13/00 , H04L12/801 , H04L12/811 , H04L12/911 , H04L29/06 , H04L29/08 , H04M11/08 , H04N7/50 , H04N7/56 , H04N21/21 , H04N21/23 , H04N21/6377 , H04N21/658 , H04Q11/04 , H04J3/22
CPC分类号： H04L47/25 , H04L12/54 , H04L47/10 , H04L49/90 , H04L49/9047 , H04M11/08 , H04N19/115 , H04N19/152 , H04N19/164 , H04N19/184 , H04N19/61 , H04N21/21 , H04N21/23 , H04N21/6377 , H04N21/658 , H04N7/56 , H04Q11/04 , H04N19/146 , H04N19/50
摘要： A method and system for information processing in a bidirectional information transmission system, particularly for transmitting information in accordance with a change in a transmission capacity of a transmission line. A system is provided which can change an information transmission rate in accordance with a room capacity of a transmission line. This information transmission system includes a plurality of information providers, a plurality of information receivers, an information storage and distribution unit connected to the information providers and receivers, and a plurality of information transmission lines for information transmission between the information providers and receivers and the information storage and distribution unit, wherein the information transmission rate of each information transmission line is changed.
摘要翻译：一种双向信息传输系统中信息处理的方法和系统，特别是用于根据传输线的传输容量的变化发送信息。提供一种可以根据传输线的房间容量改变信息传输速率的系统。该信息传输系统包括多个信息提供者，多个信息接收者，连接到信息提供者和接收者的信息存储和分配单元，以及用于在信息提供者和接收者之间进行信息传输的多条信息传输线以及信息存储和分配单元，其中每个信息传输线的信息传输速率改变。

16. 发明授权

US5430733A Digital transmission system for multiplexing and demultiplexing signals 失效
标题翻译：用于复用和解复用信号的数字传输系统
公开(公告)号：US5430733A
公开(公告)日：1995-07-04
申请号：US452511
申请日：1989-12-19
申请人： Yoshitaka Takasaki
发明人： Yoshitaka Takasaki
IPC分类号： H04L25/49 , H04J3/00
CPC分类号： H04L25/4908
摘要： Data transmission and recovery, in either the optical or the electrical domain, can be accomplished with mBnB encoding with the violation of one or more of the n code pulses for multiplexing overhead signals, with a carried clock being indicated by periodic fixed position transitions, and with both extraction of the clock and demultiplexing of the overhead signals being accomplished with only logical processing and signal delay. For the above, transmission and processing in only the optical domain can be easily obtained as well as a circuitry that can be constructed cheaply and on a small scale, particularly by integration on a single substrate. The logical processing involves logical combinations of two or more of the received encoded signal, a delay of the received encoded signal, an output of a previous logical combination, and a delayed output of a previous combination, an extracted clock, and a frequency division or a frequency multiplication of an extracted clock.
摘要翻译：在光或电域中的数据传输和恢复可以用mBnB编码来实现，其中违反一个或多个用于复用开销信号的n个码脉冲，携带时钟由周期性固定位置转换指示，以及同时提取时钟并且只用逻辑处理和信号延迟来完成开销信号的解复用。对于上述，可以容易地获得仅在光学域中的传输和处理，以及可以廉价且小规模地构建的电路，特别是通过集成在单个基板上。逻辑处理涉及接收到的编码信号中的两个或更多个，接收到的编码信号的延迟，先前逻辑组合的输出和先前组合的延迟输出，提取的时钟和分频或提取时钟的倍频。

17. 发明授权

US4204176A Variable equalizer 失效
标题翻译：可变均衡器
公开(公告)号：US4204176A
公开(公告)日：1980-05-20
申请号：US893014
申请日：1978-04-03
申请人： Yoshitaka Takasaki , Yasuhiro Kita , Junichi Nakagawa , Kohei Ishizuka
发明人： Yoshitaka Takasaki , Yasuhiro Kita , Junichi Nakagawa , Kohei Ishizuka
IPC分类号： H03H7/01 , H04B3/14 , H03H7/14
CPC分类号： H04B3/145
摘要： A variable equalizer whose frequency characteristic varies in a range of 1-1/Y(f).sup.2when the gain x of a variable amplifier varies from 0 (zero) to .infin. (infinity), and which reduces the number of shaping networks for the variable frequency characteristic.It is constructed of a forward pass circuit which consists of a variable amplifier and a frequency-dependent first circuit connected in the order mentioned between input and output terminals, a feedback pass circuit which is dependent upon the frequency and which feeds-back an output of the variable amplifier to an input thereof, and a feed forward pass circuit which is independent of the frequency and which feeds forward part of the input of the variable amplifier to an output of the first circuit.
摘要翻译：当可变放大器的增益x从0（零）到INFINITY（无穷大）变化时，其频率特性在1-1 / Y（f）2的范围内变化的可变均衡器，并且这减少了可变频率特性。它由正向电路构成，该正向电路由可变放大器和按照输入和输出端之间的顺序连接的频率依赖的第一电路组成，反馈通道电路取决于频率，并且反馈输出可变放大器到其输入端，以及前馈传输电路，其独立于频率，并且将可变放大器的输入的前部部分馈送到第一电路的输出。

18. 发明授权

US5140453A Optical receiving method utilizing polarization diversity and apparatus for carrying out the same 失效
标题翻译：利用极化分集的光接收方法及其执行装置
公开(公告)号：US5140453A
公开(公告)日：1992-08-18
申请号：US166984
申请日：1988-03-11
申请人： Hideaki Tsushima , Katsuyuki Imoto , Hirohisa Sano , Akihiko Takase , Yoshitaka Takasaki , Minoru Maeda
发明人： Hideaki Tsushima , Katsuyuki Imoto , Hirohisa Sano , Akihiko Takase , Yoshitaka Takasaki , Minoru Maeda
IPC分类号： H04B10/148
CPC分类号： H04B10/61 , H04B10/614 , H04B10/64
摘要： An optical receiving method utilizing polarization diversity is disclosed in which first and second reference lightwaves having different frequencies and having polarization planes substantially perpendicular to each other, are combined with a signal lightwave to form a combined lightwave. The combined lightwave is subjected to heterodyne detection to obtain a detection signal and the detection signal is separated into first and second intermediate-frequency signals having different carrier frequencies. The first and second intermediate-frequency signals are converted into first and second baseband signals, respectively, and the first and second baseband signals are added to obtain an output signal.
摘要翻译：公开了一种利用极化分集的光接收方法，其中具有不同频率的第一和第二参考光波具有彼此基本垂直的偏振面，与信号光波组合以形成组合的光波。对组合的光波进行外差检测以获得检测信号，并将检测信号分离成具有不同载波频率的第一和第二中频信号。第一和第二中频信号分别转换为第一和第二基带信号，并且相加第一和第二基带信号以获得输出信号。

19. 发明授权

US5023604A Communication system 失效
标题翻译：通讯系统
公开(公告)号：US5023604A
公开(公告)日：1991-06-11
申请号：US233096
申请日：1988-08-17
申请人： Akihiko Takase , Yoshitaka Takasaki
发明人： Akihiko Takase , Yoshitaka Takasaki
IPC分类号： H04L12/52 , H04Q11/04
CPC分类号： H04Q11/04 , H04L12/52
摘要： The invention provides a communication method and system for use in a network for digital data exchange/transfer through a circuit switched network. According to the method and system, a call is given the attribute of an intermittent transfer mode, and a device for identifying attributes is provided on network controls in connection paths so that the network control establishes a path only in response to a data transfer request from identified call and releases the path when the call is held on standby for data transfer.
摘要翻译：本发明提供一种在网络中用于通过电路交换网络进行数字数据交换/传输的通信方法和系统。根据该方法和系统，给予间歇传送模式的属性的呼叫，并且在连接路径中的网络控制上提供用于识别属性的设备，使得网络控制仅响应于来自当呼叫持续待机以进行数据传输时，识别呼叫并释放路径。

20. 发明授权

US4796281A Digital signal transmission system 失效
标题翻译：数字信号传输系统
公开(公告)号：US4796281A
公开(公告)日：1989-01-03
申请号：US919458
申请日：1986-10-16
申请人： Yoshitaka Takasaki
发明人： Yoshitaka Takasaki
IPC分类号： H04J3/06 , H04J3/07 , H04L25/05 , H04N7/52 , H04L7/00
CPC分类号： H04L25/05 , H04J3/073 , H04N21/234309 , H04N21/440218
摘要： A digital signal transmission system which converts first digital signals having a given bit rate into second digital signals having a predetermined bit rate to transmit them. The first digital signals are written into a buffer memory at a bit rate of the first digital signals, and the written signals are read from the first buffer memory at a bit rate of said second digital signals. The reading of the digital signals is carried out with a clock signal which consists of synchronous portions that read the written signals at any time and asynchronous portions that read the written signals depending upon the condition of the written signals. The second digital signals are sent after adding a data signal to the asynchronous portions of the digital signals. A second buffer memory receives the sent second digital signals and temporarily stores them by writing the second digital signals at the bit rate of said second digital signals, and reading the written signals from the second buffer memory at a bit rate of the third digital signals, the reading of the third digital signals depending upon signals of the asynchronous portions of the second digital signals.
摘要翻译：一种数字信号传输系统，其将具有给定比特率的第一数字信号转换成具有预定比特率的第二数字信号以发送它们。第一数字信号以第一数字信号的比特率写入缓冲存储器，并且以所述第二数字信号的比特率从第一缓冲存储器读取写入的信号。数字信号的读取由时钟信号执行，该时钟信号由随时读取写入信号的同步部分和根据写入信号的条件读取写入信号的异步部分组成。在将数据信号添加到数字信号的异步部分之后发送第二数字信号。第二缓冲存储器接收所发送的第二数字信号，并通过以所述第二数字信号的比特率写入第二数字信号来临时存储它们，并以第三数字信号的比特率从第二缓冲存储器读取写入的信号，根据第二数字信号的异步部分的信号读取第三数字信号。

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