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11. 发明授权

US06388929B1 Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same 失效
标题翻译：基于操作测试执行冗余修复的半导体存储器件和具有该半导体集成电路器件
公开(公告)号：US06388929B1
公开(公告)日：2002-05-14
申请号：US09906654
申请日：2001-07-18
申请人： Hiroki Shimano , Kazutami Arimoto
发明人： Hiroki Shimano , Kazutami Arimoto
IPC分类号： G11C2900
CPC分类号： G11C29/70 , G11C29/44
摘要： A BIST circuit conducts an operation test on a memory cell array to detect a defective memory cell when power is turned on. On the basis of a result of the operation test, the BIST circuit generates a redundancy code indicative of a defect address corresponding to a defective memory cell. The redundancy code is transmitted to a repair determining circuit in a decoding circuit. The repair determining circuit stores the redundancy code in a volatile manner during the power is on. When an input address coincides with the redundancy code to be stored on the inside, the repair determining circuit executes an access to a corresponding spare memory cell area.
摘要翻译： BIST电路在存储单元阵列上进行操作测试，以在电源接通时检测缺陷存储单元。基于操作测试的结果，BIST电路产生指示与缺陷存储单元对应的缺陷地址的冗余码。冗余码被传送到解码电路中的修复确定电路。修复确定电路在电源接通期间以易失性的方式存储冗余码。当输入地址与要存储在内部的冗余码一致时，修复确定电路执行对相应的备用存储单元区的访问。

12. 发明授权

US07480168B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07480168B2
公开(公告)日：2009-01-20
申请号：US11819583
申请日：2007-06-28
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/24
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑并入的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

13. 发明授权

US07139208B2 Refresh-free dynamic semiconductor memory device 失效
公开(公告)号：US07139208B2
公开(公告)日：2006-11-21
申请号：US11165273
申请日：2005-06-24
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C7/20 , G11C5/14
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

14. 发明授权

US06909658B2 Semiconductor memory device with row selection control circuit 失效
标题翻译：具有行选择控制电路的半导体存储器件
公开(公告)号：US06909658B2
公开(公告)日：2005-06-21
申请号：US10842465
申请日：2004-05-11
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C2207/104
摘要： A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.
摘要翻译：将自刷新定时器持续设置为使周期性地刷新请求信号FAY活动的操作状态。当在刷新请求信号FAY和外部施加的读取/写入命令之间发生争用时，行选择相关电路/命令生成相关电路控制与行相关的控制信号，使得在例如读取或写入命令之后执行刷新操作写操作结束。子存储阵列SMA被划分为比常规情况更小的刷新周期，并且刷新周期在更短的时间段内结束。因此，可以在读周期时间内完成读操作和刷新操作。可以实现可以使用与SRAM的控制一样简单的DRAM内核。

15. 发明授权

US06781915B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06781915B2
公开(公告)日：2004-08-24
申请号：US10274872
申请日：2002-10-22
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C800
CPC分类号： G11C7/18 , G11C11/405 , G11C11/4097 , G11C2211/4013 , H01L27/108 , H01L27/10897
摘要： Memory cells are arranged such that one-bit data is stored by two-bit memory cells. The cell plate electrode of the memory cell capacitor and the gate electrode of the memory cell transistor are formed in the same manufacturing step. The amplitude of an isolation control signal applied to a bit line isolation gate connecting the bit line and the sense amplifier is restricted, and the word line is driven according to a negative voltage non-boosted word line scheme. A well region where a memory block is formed and a well region where the isolation gate is formed are separately provided, and separate bias voltages are applied thereto. Thus, a DRAM (dynamic random access memory)-based logic merged memory is implemented without degrading dielectric breakdown characteristics of the gate insulating film.
摘要翻译：存储单元被布置成使得一位数据由两位存储器单元存储。存储单元电容器的单元板电极和存储单元晶体管的栅极形成在相同的制造步骤中。施加到连接位线和读出放大器的位线隔离栅的隔离控制信号的幅度受到限制，并且字线根据负电压非升压字线方案被驱动。形成存储块的阱区和形成隔离栅的阱区分开设置，并且分别施加偏置电压。因此，实现基于DRAM（动态随机存取存储器）的逻辑合并存储器而不降低栅极绝缘膜的绝缘击穿特性。

16. 发明授权

US06608795B2 Semiconductor device including memory with reduced current consumption 失效
公开(公告)号：US06608795B2
公开(公告)日：2003-08-19
申请号：US10277879
申请日：2002-10-23
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4082 , G11C11/4087 , G11C2207/104
摘要： When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a system LSI with reduced current consumption in the memory array can be realized.

17. 发明申请

US20090103353A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090103353A1
公开(公告)日：2009-04-23
申请号：US12338219
申请日：2008-12-18
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/24 , G11C5/14 , G11C8/08
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑合并的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

18. 发明申请

US20080137394A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20080137394A1
公开(公告)日：2008-06-12
申请号：US12000343
申请日：2007-12-12
申请人： Hiroki Shimano , Fukashi Morishita , Kazutami Arimoto
发明人： Hiroki Shimano , Fukashi Morishita , Kazutami Arimoto
IPC分类号： G11C5/06
CPC分类号： G11C8/16 , G11C5/063 , G11C7/12 , G11C7/18 , G11C11/405 , G11C11/4094 , G11C11/4097 , G11C2211/4016 , H01L21/84 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.
摘要翻译：一个存储单元由第一端口存取晶体管，第二端口存取晶体管和与这些存取晶体管共同耦合的存储晶体管形成。第一端口存取晶体管耦合到存储晶体管的第一电极，第二端口存取晶体管耦合到存储晶体管的第三电极。当分别选择第一和第二端口字线时，这些第一和第二端口存取晶体管进入选择状态，以将相应的存储晶体管的相应的第二和第三电极分别耦合到第一和第二端口位线。可以提供一种双端口存储单元，其可扩展性可以在一个过程中跟随小型化。

19. 发明授权

US06925022B2 Refresh-free dynamic semiconductor memory device 失效
标题翻译：无刷新动态半导体存储器件
公开(公告)号：US06925022B2
公开(公告)日：2005-08-02
申请号：US10229035
申请日：2002-08-28
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/403 , G11C11/405 , G11C11/406 , G11C11/408 , G11C11/409 , G11C29/02 , G11C29/04 , G11C29/14 , G11C7/20
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.
摘要翻译：在数据保持模式下，在正常操作模式下的一位/一个单元方案中的数据存储以双位模式重新排列成数据存储，其中数据以一位/双位单元方式存储。在双电池模式中，两个子字线同时被驱动到选择状态，并且在一对位线上读出存储器单元的存储数据，以执行感测操作。因此，可以增加读出电压以改善用于延长刷新间隔的数据保持特性，导致数据保持模式中的功耗降低。

20. 发明授权

US06898137B2 Semiconductor memory device with high-speed sense amplifier 有权
标题翻译：具有高速读出放大器的半导体存储器件
公开(公告)号：US06898137B2
公开(公告)日：2005-05-24
申请号：US10403009
申请日：2003-04-01
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： H01L27/108 , G11C7/06 , G11C7/12 , G11C7/14 , G11C11/401 , G11C11/4091 , G11C11/4099 , H01L21/8242 , G11C7/02
CPC分类号： G11C11/4099 , G11C7/062 , G11C7/12 , G11C7/14 , G11C11/4091
摘要： In a Vss precharge scheme, dummy cells including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line are arranged in complementary bit lines. In a waiting state, H level data is written in each dummy cell from the Vccs power supply line. Before row activation is started and a normal word line is selected, a dummy word line is driven to a selected state, and the H level data is read from each dummy cell. Therefore, charge in equal amounts is injected to the complementary bit lines, and a shift from a Vss level to the same potential occurs. A sense amplifier uses the potential as a reference voltage to amplify and detect a potential difference between bit lines.
摘要翻译：在Vss预充电方案中，包括位线触点，存储节点触点和连接到Vcc电源线的第三触点的虚拟单元被布置在互补位线中。在等待状态下，从Vcc电源线将H电平数据写入每个虚拟单元。在行激活开始并且选择正常字线之前，将虚拟字线驱动到所选状态，并且从每个虚拟单元读取H电平数据。因此，等量的电荷被注入到互补位线，并且发生从Vss电平到相同电位的偏移。读出放大器使用该电位作为参考电压来放大和检测位线之间的电位差。

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