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    • 12. 发明申请
    • DETERMINING AND ANALYZING INTEGRATED CIRCUIT YIELD AND QUALITY
    • 确定和分析集成电路的质量和质量
    • US20090210183A1
    • 2009-08-20
    • US12415806
    • 2009-03-31
    • Janusz RajskiGang ChenMartin KeimNagesh TamarapalliManish SharmaHuaxing Tang
    • Janusz RajskiGang ChenMartin KeimNagesh TamarapalliManish SharmaHuaxing Tang
    • G06F19/00
    • G06F11/2273G01R31/01G01R31/2846G01R31/2853G01R31/2894G01R31/31704G01R31/31835
    • Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.
    • 本文公开了用于计算,分析和改进集成电路产量和质量的方法,装置和系统。 例如,在本文公开的一个示例性方法中,从设计用于电子设备中的功能使用的集成电路的处理测试响应中接收信息。 在该实施例中,该信息表示在集成电路测试期间观察到的集成电路故障以及导致集成电路故障的可能的产量限制因素。 通过统计分析接收的信息来确定集成电路中的一个或多个可能的屈服限制因素实际上引起集成电路故障的概率。 报告了一个或多个可能的屈服限制因素实际上导致集成电路故障的概率。 还公开了包括用于使计算机执行任何所述方法的计算机可执行指令的有形计算机可读介质。
    • 13. 发明授权
    • Sensor array using sail
    • 传感器阵列使用帆
    • US07470544B2
    • 2008-12-30
    • US11138619
    • 2005-05-26
    • Manish Sharma
    • Manish Sharma
    • G03F7/00H01B13/00C03C15/00G01R31/00G01N1/00
    • G01N27/4145Y10T436/25
    • Provided is a sensor array and a method of forming the same. The sensor array includes an array of apertures etched into a 3D patterned resist layer to expose areas of one or more agents and/or reagents deposited on a substrate. The sensor is formed using a Self-Aligned Imprint Lithography (“SAIL”) method, a process that allows for a one-time deposition of all required materials followed by a series of etching/cleaning steps. The location of reagents on the sensor template, as well as the concentration gradient of each reagent, may be controlled through the sensor manufacturing process. Bores of a single reagent, or bores containing two or more reagents, may be formed using the SAIL process.
    • 提供一种传感器阵列及其形成方法。 传感器阵列包括刻蚀成3D图案化抗蚀剂层的孔的阵列,以暴露沉积在基底上的一种或多种试剂和/或试剂的区域。 传感器使用自对准印迹光刻(“SAIL”)方法形成,该方法允许一次性沉积所有所需材料,然后进行一系列蚀刻/清洁步骤。 传感器模板上的试剂位置以及各试剂的浓度梯度可通过传感器制造过程进行控制。 可以使用SAIL方法形成单个试剂的孔或包含两种或更多种试剂的孔。
    • 18. 发明授权
    • Process for making a memory structure
    • 制作内存结构的过程
    • US07138341B1
    • 2006-11-21
    • US10886963
    • 2004-07-07
    • Manish Sharma
    • Manish Sharma
    • H01L21/302H01L21/461
    • H01L21/31144H01L21/32139H01L27/222H01L43/12
    • An exemplary method for making a memory structure comprises forming a first hard mask layer, forming at least one mask layer above the first hard mask layer, patterning the at least one mask layer, etching the at least one mask layer to form an opening having a first lateral width, and a second lateral width different than the first lateral width, forming a second hard mask layer having substantially the first and second lateral widths in the opening, and etching the first hard mask layer using at least one of the lateral widths of the second hard mask layer.
    • 用于制造存储器结构的示例性方法包括形成第一硬掩模层,在第一硬掩模层上方形成至少一个掩模层,图案化至少一个掩模层,蚀刻至少一个掩模层以形成具有 第一横向宽度和与第一横向宽度不同的第二横向宽度,形成在开口中具有基本上第一和第二横向宽度的第二硬掩模层,并且使用横向宽度的至少一个来蚀刻第一硬掩模层 第二个硬掩模层。