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11. 发明授权

US08373072B2 Printed circuit board 有权
标题翻译：印刷电路板
公开(公告)号：US08373072B2
公开(公告)日：2013-02-12
申请号：US12501931
申请日：2009-07-13
申请人： Daisuke Iguchi , Kanji Otsuka , Yutaka Akiyama
发明人： Daisuke Iguchi , Kanji Otsuka , Yutaka Akiyama
IPC分类号： H05K1/03
CPC分类号： H05K9/0084 , H05K1/0218 , H05K1/0234 , H05K1/167 , H05K3/403 , H05K2201/0187 , H05K2201/0215 , H05K2201/09309
摘要： A printed circuit board includes a ground layer, a power source layer, a signal wiring layer, an insulating layer and an electromagnetic radiation suppressing member. The power source layer is provided to be opposed to the ground layer. The signal wiring layer transmits a signal in a predetermined frequency domain. The insulating layer insulates the ground layer, the power source layer and the signal wiring layer from one another. The electromagnetic radiation suppressing member is provided to cover a circumferential edge of the insulating layer. The electromagnetic radiation suppressing member has a negative dielectric constant and a positive magnetic permeability in a frequency domain including the predetermined frequency domain.
摘要翻译：印刷电路板包括接地层，电源层，信号布线层，绝缘层和电磁辐射抑制构件。电源层设置成与接地层相对。信号布线层发送预定频域的信号。绝缘层使接地层，电源层和信号布线层彼此绝缘。电磁辐射抑制构件被设置成覆盖绝缘层的周缘。电磁辐射抑制构件在包括预定频域的频域中具有负介电常数和正磁导率。

12. 发明授权

US07906840B2 Semiconductor integrated circuit package, printed circuit board, semiconductor apparatus, and power supply wiring structure 有权
标题翻译：半导体集成电路封装，印刷电路板，半导体装置和电源布线结构
公开(公告)号：US07906840B2
公开(公告)日：2011-03-15
申请号：US12204677
申请日：2008-09-04
申请人： Kanji Otsuka , Yutaka Akiyama
发明人： Kanji Otsuka , Yutaka Akiyama
IPC分类号： H01L23/02
CPC分类号： H05K1/0231 , H01L23/50 , H01L23/5286 , H01L23/552 , H01L23/66 , H01L2223/6638 , H01L2224/16225 , H01L2924/19051 , H01L2924/3011 , H05K1/0263 , H05K2201/09672 , H05K2201/10545 , H05K2201/10734
摘要： A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.
摘要翻译：提供了一种半导体集成电路封装，印刷电路板，半导体装置和电源布线结构，即使在高频带宽下也能够实现稳定的电源和接地布线而不引起共振。在封装的内部，电源布线和接地布线构成一对布线结构，其中电源布线和接地布线以预定的间隔并置，以便在它们之间建立电磁耦合。多个对布线结构以这样的方式组合，即当在与布线延伸方向垂直的截面中观察时，该对布线组件呈现交错（方格）的结构。优选地，像封装一样，硅芯片和印刷电路板中的每一个具有配置在内部的配线结构。

13. 发明申请

US20080310521A1 Signal transmission circuit and signal transmission system 有权
标题翻译：信号传输电路和信号传输系统
公开(公告)号：US20080310521A1
公开(公告)日：2008-12-18
申请号：US12153786
申请日：2008-05-23
申请人： Kanji Otsuka , Yutaka Akiyama
发明人： Kanji Otsuka , Yutaka Akiyama
IPC分类号： H04B3/00 , H04L27/00 , H04L25/00
CPC分类号： H04L25/028
摘要： A signal transmission circuit includes a transmitting circuit for outputting a transmitting signal to a transmission line, a parallel circuit including a capacitor and a first resistance connected between an output terminal of the transmitting circuit and the transmission line, and a series circuit including an inductor and a second resistance connected between an output side of the parallel circuit and a ground.
摘要翻译：信号传输电路包括用于向传输线输出发送信号的发送电路，包括电容器的并联电路和连接在发送电路的输出端子与传输线路之间的第一电阻，以及串联电路，包括电感器和连接在并联电路的输出侧和地之间的第二电阻。

14. 发明授权

US07804111B2 Semiconductor device and method for adjusting characteristics thereof 有权
标题翻译：用于调整其特性的半导体器件和方法
公开(公告)号：US07804111B2
公开(公告)日：2010-09-28
申请号：US12083573
申请日：2006-10-10
申请人： Kanji Otsuka , Munekazu Takano , Fumio Mizuno , Saburo Yokokura , Tsuneo Ito , Yuko Tanba , Yutaka Akiyama
发明人： Kanji Otsuka , Munekazu Takano , Fumio Mizuno , Saburo Yokokura , Tsuneo Ito , Yuko Tanba , Yutaka Akiyama
IPC分类号： H01L29/94
CPC分类号： H03K5/156 , H01L23/642 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/19041 , H01L2924/19051 , H01L2924/30107 , H01L2924/3011 , H03K2005/00026 , H03K2217/0018 , H04L25/085 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection 20 for transmission of signals, a MOS capacitance element 10 having a gate electrode connected to the signal-transmission interconnection 20, a first voltage-applying interconnection 30 connected to a source and a drain of the MOS capacitance element 10 and applying a voltage to the source and the drain of the MOS capacitance element 10, a second voltage-applying interconnection 40 connected to a well of the MOS capacitance element 10, and applying a voltage to the well of said first MOS capacitance element 10. Jitters occurring in the signal-transmission interconnection 20 can be adjusted by adjusting each of voltages of the first voltage-applying interconnection 30 and the second voltage-applying interconnection 40.
摘要翻译：本发明的目的是提供一种半导体器件，其包括优选用于传输高频信号的信号传输互连和调整上述信号传输互连特性的能力。根据本发明的半导体器件包括用于传输信号的信号传输互连20，具有连接到信号传输互连20的栅电极的MOS电容元件10，连接到源的第一施加电压互连30 和MOS电容元件10的漏极，并向MOS电容元件10的源极和漏极施加电压，连接到MOS电容元件10的阱的第二施加电压互连40，并向可以通过调节第一施加电压互连30和第二施加电压互连40的每个电压来调节发生在信号传输互连20中的抖动。

15. 发明申请

US20110255323A1 MEMORY/LOGIC CONJUGATE SYSTEM 失效
标题翻译：内存/逻辑连接系统
公开(公告)号：US20110255323A1
公开(公告)日：2011-10-20
申请号：US12977243
申请日：2010-12-23
申请人： Kanji Otsuka , Tsuneo Ito , Yoichi Sato , Masahiro Yoshida , Shigeru Yamamoto , Takeshi Koyama , Yuko Tanba , Yutaka Akiyama
发明人： Kanji Otsuka , Tsuneo Ito , Yoichi Sato , Masahiro Yoshida , Shigeru Yamamoto , Takeshi Koyama , Yuko Tanba , Yutaka Akiyama
IPC分类号： G11C5/06
CPC分类号： G06F13/4022 , G11C5/02 , G11C7/1006 , G11C2213/71
摘要： There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.
摘要翻译：存在带宽瓶颈的问题，因为使用交叉开关来应对规模的增加。在根据本发明的存储器/逻辑共轭系统的示例中，多个集群存储器芯片，每个集群存储器芯片包括多个集群存储器20，其包括布置在集群中的基本单元10，基本单元10包括存储器电路，以及控制多个集群存储器的控制器芯片是三维堆叠的，沿着多个集群存储器芯片的堆叠方向定位的多个集群存储器20和控制器芯片经由多片11电连接到控制器芯片，通孔中，任意一个基本单元10通过多轴11从控制器芯片直接访问，从而将真值数据写入其中，从而将任意的基本单元10切换到逻辑电路作为共轭。

16. 发明授权

US08736074B2 Multi chip semiconductor device 有权
标题翻译：多芯片半导体器件
公开(公告)号：US08736074B2
公开(公告)日：2014-05-27
申请号：US12624490
申请日：2009-11-24
申请人： Daisuke Iguchi , Kanji Otsuka , Yutaka Akiyama
发明人： Daisuke Iguchi , Kanji Otsuka , Yutaka Akiyama
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/66 , H01L24/17 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2223/6638 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2225/0651 , H01L2225/06517 , H01L2225/06531 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area.
摘要翻译：根据本发明的一个方面，半导体器件包括具有开口面积的衬底，第一半导体芯片和第二半导体芯片。第一半导体芯片具有用于高速连通的第一电极，并且设置在基板上的开口区域周围。第二半导体芯片具有用于功率和低速连通的第二电极和第三电极，并且设置在第一半导体芯片上，使得第一电极通过静电耦合和电介质耦合与第二电极耦合，第三电极面向开放区域。

17. 发明授权

US08305789B2 Memory/logic conjugate system 失效
标题翻译：存储器/逻辑共轭系统
公开(公告)号：US08305789B2
公开(公告)日：2012-11-06
申请号：US12977243
申请日：2010-12-23
申请人： Kanji Otsuka , Tsuneo Ito , Yoichi Sato , Masahiro Yoshida , Shigeru Yamamoto , Takeshi Koyama , Yuko Tanba , Yutaka Akiyama
发明人： Kanji Otsuka , Tsuneo Ito , Yoichi Sato , Masahiro Yoshida , Shigeru Yamamoto , Takeshi Koyama , Yuko Tanba , Yutaka Akiyama
IPC分类号： G11C5/06
CPC分类号： G06F13/4022 , G11C5/02 , G11C7/1006 , G11C2213/71
摘要： A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.
摘要翻译：发生带宽瓶颈是因为使用横杠开关来应对规模的增加。根据本发明的存储器/逻辑共轭系统，多个集群存储器芯片，每个集群存储器芯片包括多个集群存储器20，集群存储器20包括布置在集群中的基本单元10，基本单元10包括存储器电路，以及控制芯片，多个集群存储器是三维堆叠的，沿着多个集群存储器芯片的堆叠方向定位的多个集群存储器20和控制器芯片经由包括通孔的多通道11电耦合到控制器芯片，基本单元10中的任意一个基本单元10通过多轴11从控制器芯片直接访问，从而将真值数据写入其中，并且由此将任意基本单元10切换到逻辑电路作为共轭。

18. 发明申请

US20100013318A1 PRINTED CIRCUIT BOARD 有权
标题翻译：印刷电路板
公开(公告)号：US20100013318A1
公开(公告)日：2010-01-21
申请号：US12501931
申请日：2009-07-13
申请人： Daisuke Iguchi , Kanji Otsuka , Yutaka Akiyama
发明人： Daisuke Iguchi , Kanji Otsuka , Yutaka Akiyama
IPC分类号： H05K9/00
CPC分类号： H05K9/0084 , H05K1/0218 , H05K1/0234 , H05K1/167 , H05K3/403 , H05K2201/0187 , H05K2201/0215 , H05K2201/09309
摘要： A printed circuit board includes a ground layer, a power source layer, a signal wiring layer, an insulating layer and an electromagnetic radiation suppressing member. The power source layer is provided to be opposed to the ground layer. The signal wiring layer transmits a signal in a predetermined frequency domain. The insulating layer insulates the ground layer, the power source layer and the signal wiring layer from one another. The electromagnetic radiation suppressing member is provided to cover a circumferential edge of the insulating layer. The electromagnetic radiation suppressing member has a negative dielectric constant and a positive magnetic permeability in a frequency domain including the predetermined frequency domain.
摘要翻译：印刷电路板包括接地层，电源层，信号布线层，绝缘层和电磁辐射抑制构件。电源层设置成与接地层相对。信号布线层发送预定频域的信号。绝缘层使接地层，电源层和信号布线层彼此绝缘。电磁辐射抑制构件被设置成覆盖绝缘层的周缘。电磁辐射抑制构件在包括预定频域的频域中具有负介电常数和正磁导率。

19. 发明申请

US20090108955A1 Semiconductor Device and Method for Adjusting Characteristics Thereof 有权
标题翻译：半导体器件及其特性调整方法
公开(公告)号：US20090108955A1
公开(公告)日：2009-04-30
申请号：US12083573
申请日：2006-10-10
申请人： Kanji Otsuka , Munekazu Takano , Fumio Mizuno , Saburo Yokokura , Tsuneo Ito , Yuko Tanba , Yutaka Akiyama
发明人： Kanji Otsuka , Munekazu Takano , Fumio Mizuno , Saburo Yokokura , Tsuneo Ito , Yuko Tanba , Yutaka Akiyama
IPC分类号： H03K5/1252 , H01L29/94
CPC分类号： H03K5/156 , H01L23/642 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/19041 , H01L2924/19051 , H01L2924/30107 , H01L2924/3011 , H03K2005/00026 , H03K2217/0018 , H04L25/085 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection 20 for transmission of signals, a MOS capacitance element 10 having a gate electrode connected to the signal-transmission interconnection 20, a first voltage-applying interconnection 30 connected to a source and a drain of the MOS capacitance element 10 and applying a voltage to the source and the drain of the MOS capacitance element 10, a second voltage-applying interconnection 40 connected to a well of the MOS capacitance element 10, and applying a voltage to the well of said first MOS capacitance element 10. Jitters occurring in the signal-transmission interconnection 20 can be adjusted by adjusting each of voltages of the first voltage-applying interconnection 30 and the second voltage-applying interconnection 40.
摘要翻译：本发明的目的是提供一种半导体器件，其包括优选用于传输高频信号的信号传输互连和调整上述信号传输互连特性的能力。根据本发明的半导体器件包括用于传输信号的信号传输互连20，具有连接到信号传输互连20的栅电极的MOS电容元件10，连接到源的第一施加电压互连30 和MOS电容元件10的漏极，并向MOS电容元件10的源极和漏极施加电压，连接到MOS电容元件10的阱的第二施加电压互连40，并向可以通过调节第一施加电压互连30和第二施加电压互连40的每个电压来调节发生在信号传输互连20中的抖动。

20. 发明授权

US08148774B2 Method of fabricating semiconductor device with a high breakdown voltage between neighboring wells 有权
标题翻译：制造相邻孔之间具有高击穿电压的半导体器件的方法
公开(公告)号：US08148774B2
公开(公告)日：2012-04-03
申请号：US12606634
申请日：2009-10-27
申请人： Hidemitsu Mori , Kazuhiro Takimoto , Toshiyuki Shou , Kenji Sasaki , Yutaka Akiyama
发明人： Hidemitsu Mori , Kazuhiro Takimoto , Toshiyuki Shou , Kenji Sasaki , Yutaka Akiyama
IPC分类号： H01L29/66 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/26513 , H01L21/823493
摘要： To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same. A semiconductor device includes a first conductivity type semiconductor substrate 1, second conductivity type first wells 2 and 3 disposed on a surface layer of the semiconductor substrate 1 with a predetermined interval between them, a first conductivity type second well 4 disposed between the first wells 2 and 3 on the surface layer of the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate, a first conductivity type third well 5 at least disposed below the second well 4 in the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate 1 and lower than that of the second well 4, and a first conductivity type fourth well 11 at least disposed below the third well 5 in the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate 1 and lower than that of the second well 4.
摘要翻译：提供一种半导体器件，其中可以通过改善第一阱之间的分离击穿电压及其制造方法来缩短第一阱之间的间隔。半导体器件包括第一导电类型半导体衬底1，设置在半导体衬底1的表面层上的第二导电类型的第一阱2和3之间的预定间隔，设置在第一阱2之间的第一导电类型第二阱4 并且在半导体衬底1的表面层上具有杂质浓度高于半导体衬底1的杂质浓度的第一导电类型第三阱5，至少设置在半导体衬底1中的第二阱4的下方并且杂质浓度更高比半导体衬底1低，而低于第二阱4，以及第一导电类型的第四阱11，其至少设置在半导体衬底1中的第三阱5的下方，其杂质浓度高于半导体衬底的杂质浓度 1且低于第二孔4的厚度。

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