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11. 发明申请

US20070187761A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070187761A1
公开(公告)日：2007-08-16
申请号：US11729241
申请日：2007-03-28
申请人： Takashi Hamada , Satoshi Murakami , Shunpei Yamazaki , Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Toru Takayama
发明人： Takashi Hamada , Satoshi Murakami , Shunpei Yamazaki , Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Toru Takayama
IPC分类号： H01L27/12
CPC分类号： H01L21/02672 , G02F1/13454 , H01L21/2022 , H01L21/3226 , H01L27/12 , H01L27/1248 , H01L27/1277 , H01L27/1288 , H01L27/3246 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78621 , H01L51/5253 , H01L51/56
摘要： The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semiconductor film to the semiconductor film containing a rare gas element by a heat treatment. Furthermore, a first impurity region and a second impurity region formed in a semiconductor layer of a first n-channel TFT are provided outside a gate electrode. A third impurity region formed in a semiconductor layer of a second n-channel TFT is provided so as to be partially overlapped with a gate electrode. A third impurity region is provided outside a gate electrode. A fourth impurity region formed in a semiconductor layer of a p-channel TFT is provided so as to be partially overlapped with a gate electrode. A fifth impurity region is provided outside a gate electrode.
摘要翻译：本发明的特征在于，在通过阻挡层使用催化元件而获得的结晶半导体膜上形成含有稀有气体元素的半导体膜，催化元素从结晶半导体膜移动到含有稀有气体元素通过热处理。此外，形成在第一n沟道TFT的半导体层中的第一杂质区域和第二杂质区域设置在栅电极的外侧。形成在第二n沟道TFT的半导体层中的第三杂质区域设置成与栅电极部分重叠。第三杂质区域设置在栅极外部。形成在p沟道TFT的半导体层中的第四杂质区域设置成与栅电极部分重叠。第五杂质区域设置在栅极外部。

12. 发明申请

US20070063147A1 Doping device 审中-公开
标题翻译：兴奋剂
公开(公告)号：US20070063147A1
公开(公告)日：2007-03-22
申请号：US11148287
申请日：2005-06-09
申请人： Shunpei Yamazaki , Junichi Koezuka , Hiroto Shinoda , Osamu Nakamura , Atsuo Isobe , Tetsuji Yamaguchi , Hiromichi Godo
发明人： Shunpei Yamazaki , Junichi Koezuka , Hiroto Shinoda , Osamu Nakamura , Atsuo Isobe , Tetsuji Yamaguchi , Hiromichi Godo
IPC分类号： H01J27/00 , H01J7/24 , H05B31/26
CPC分类号： H01L27/127 , H01J37/3171 , H01L21/2652 , H01L21/26586 , H01L21/67213 , H01L27/1214 , H01L29/78621 , H01L29/78624 , H01L2029/7863
摘要： According to the present invention, a manufacturing device of a semiconductor device provided with a device for uniformly doping with an impurity element a large area substrate capable of multiple patterns for the purpose of mass-production is provided. The present invention has a feature that a cross section of an ion current is to be a linear shape or a rectangle, and the large area substrate is moved in a direction perpendicular to a longitudinal direction of the ion current while keeping the large area substrate inclined at a predetermined tilt angle θ to the ion current. In this invention, an incident angle of an ion beam is adjusted as changing the tile angle θ. By making the large area substrate inclined to a horizontal plane, the width of the longitudinal direction of the ion current can be shortened than the length of a side of the substrate.
摘要翻译：根据本发明，提供了一种半导体器件的制造装置，其具有用于均匀掺杂杂质元素的装置，该装置能够进行批量生产的能够具有多种图案的大面积基板。本发明的特征在于，离子电流的截面为直线形状或矩形，大面积基板沿垂直于离子电流的长度方向的方向移动，同时保持大面积基板倾斜以离子电流的预定倾斜角θ。在本发明中，随着瓦片角度θ的改变，离子束的入射角被调整。通过使大面积基板倾斜于水平面，离子电流的长度方向的宽度可以比基板的一侧的长度缩短。

13. 发明申请

US20070037309A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070037309A1
公开(公告)日：2007-02-15
申请号：US11582445
申请日：2006-10-18
申请人： Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Shunpei Yamazaki , Hideaki Kuwabara
发明人： Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Shunpei Yamazaki , Hideaki Kuwabara
IPC分类号： H01L21/00
CPC分类号： H01L29/78696 , H01L21/02532 , H01L21/02672 , H01L21/02675 , H01L27/1277 , H01L27/1296 , H01L29/66757 , H01L29/78621 , Y10S257/913
摘要： The TFT electric characteristic is ready to be influenced by the channel region in the neighborhood of an interface between a semiconductor and a gate insulating film. The present invention provides TFTs reduced in electric characteristic deviations and a method for manufacturing the same. The invention forms a region or layer containing an inactive element, or rear gas element, in the channel region. As shown in FIG. 1, a rear gas element is contained at least in an upper layer of the channel region.
摘要翻译： TFT电气特性准备好受到半导体和栅极绝缘膜之间的界面附近的沟道区的影响。本发明提供了减少电特性偏差的TFT及其制造方法。本发明在通道区域中形成含有非活性元件或后气体元件的区域或层。如图所示。如图1所示，后气体元件至少包含在通道区域的上层中。

14. 发明申请

US20050017246A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050017246A1
公开(公告)日：2005-01-27
申请号：US10890234
申请日：2004-07-14
申请人： Keiichi Sekiguchi , Junichi Koezuka , Yasuyuki Arai , Shunpei Yamazaki
发明人： Keiichi Sekiguchi , Junichi Koezuka , Yasuyuki Arai , Shunpei Yamazaki
IPC分类号： H01L21/77 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/04 , H01L31/036
CPC分类号： H01L27/1214 , H01L27/1203 , H01L27/127 , H01L29/78624 , H01L29/78645 , H01L29/78675 , H01L29/78696 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05548 , H01L2224/05569 , H01L2224/05572 , H01L2224/16225 , H01L2224/48091 , H01L2224/73265 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to a part of a first region overlapped with the gate electrode with the gate insulating film therebetween in the active layer and a second region but the first region in the active layer by adding the impurity to the active layer from one oblique direction; and the second region is situated in the one direction relative to the first region.
摘要翻译：本发明提供了一种制造半导体器件的方法，通过该方法，提供了包括有源层，与有源层接触的栅极绝缘膜和与有源层重叠的栅极与其间的栅极绝缘膜的晶体管。在有源层和第二区域之间，与栅电极重叠的第一区域的一部分添加杂质，而通过从有源层向一个倾斜方向添加杂质，而在有源层中添加杂质 ; 并且第二区域相对于第一区域位于一个方向上。

15. 发明授权

US09240488B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US09240488B2
公开(公告)日：2016-01-19
申请号：US12968338
申请日：2010-12-15
申请人： Shunpei Yamazaki , Junichi Koezuka
发明人： Shunpei Yamazaki , Junichi Koezuka
IPC分类号： H01L29/786 , H01L21/02
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/425 , H01L21/426 , H01L21/823418 , H01L29/24 , H01L29/36 , H01L29/66969
摘要： A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation. In the transistor including an oxide semiconductor, oxygen-defect-inducing factors are introduced (added) into an oxide semiconductor layer, whereby the resistance of a source and drain regions are selectively reduced. Oxygen-defect-inducing factors are introduced into the oxide semiconductor layer, whereby oxygen defects serving as donors can be effectively formed in the oxide semiconductor layer. The introduced oxygen-defect-inducing factors are one or more selected from titanium, tungsten, and molybdenum, and are introduced by an ion implantation method.

16. 发明授权

US08952379B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08952379B2
公开(公告)日：2015-02-10
申请号：US13608044
申请日：2012-09-10
申请人： Shunpei Yamazaki , Atsuo Isobe , Hiromachi Godo , Takehisa Hatano , Sachiaki Tezuka , Suguru Hondo , Naoto Yamade , Junichi Koezuka
发明人： Shunpei Yamazaki , Atsuo Isobe , Hiromachi Godo , Takehisa Hatano , Sachiaki Tezuka , Suguru Hondo , Naoto Yamade , Junichi Koezuka
IPC分类号： H01L29/78 , H01L29/417 , H01L29/786
CPC分类号： H01L29/41733 , H01L29/78618 , H01L29/7869 , H01L29/78693
摘要： Provided is a semiconductor device in which an oxide semiconductor layer is provided; a pair of wiring layers which are provided with the gate electrode layer interposed therebetween are electrically connected to the low-resistance regions; and electrode layers are provided to be in contact with the low-resistance regions, below regions where the wiring layers are formed.
摘要翻译：提供一种半导体器件，其中提供氧化物半导体层; 设置有栅极电极层的一对布线层电连接到低电阻区域; 并且电极层设置成与低电阻区域接触，在形成布线层的区域之下。

17. 发明授权

US08735263B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US08735263B2
公开(公告)日：2014-05-27
申请号：US13346754
申请日：2012-01-10
申请人： Shunpei Yamazaki , Junichi Koezuka , Kazuya Hanaoka
发明人： Shunpei Yamazaki , Junichi Koezuka , Kazuya Hanaoka
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76254
摘要： An SOI substrate is manufactured by the following steps: a semiconductor substrate is irradiated with an ion beam in which the proportion of H2O+ to hydrogen ions (H3+) is lower than or equal to 3%, preferably lower than or equal to 0.3%, whereby an embrittled region is formed in the semiconductor substrate; a surface of the semiconductor substrate and a surface of a base substrate are disposed so as to be in contact with each other, whereby the semiconductor substrate and the base substrate are bonded; and a semiconductor layer is separated along the embrittled region from the semiconductor substrate which is bonded to the base substrate by heating the semiconductor substrate and the base substrate, so that the semiconductor layer is formed over the base substrate.
摘要翻译：通过以下步骤制造SOI衬底：用H 2 O +与氢离子（H3 +）的比例低于或等于3％，优选低于或等于0.3％的离子束照射半导体衬底，由此在半导体衬底中形成脆化区域; 将半导体基板的表面和基板的表面配置成彼此接触，由此结合半导体基板和基板; 并且通过加热半导体衬底和基底衬底而将半导体层沿着与半导体衬底分离的结合到基底衬底上，使得半导体层形成在基底衬底上。

18. 发明授权

US07316947B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07316947B2
公开(公告)日：2008-01-08
申请号：US10072931
申请日：2002-02-12
申请人： Shunpei Yamazaki , Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Koji Dairiki , Toru Mitsuki , Toru Takayama , Hideto Ohnuma , Taketomi Asami , Mitsuhiro Ichijo
发明人： Shunpei Yamazaki , Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Koji Dairiki , Toru Mitsuki , Toru Takayama , Hideto Ohnuma , Taketomi Asami , Mitsuhiro Ichijo
IPC分类号： H01L21/00
CPC分类号： H01L29/66757 , G02F1/13454 , H01L27/12 , H01L27/1277 , H01L29/78621 , H01L29/78624 , H01L29/78675 , H01L29/78678
摘要： An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device. With the present invention, a barrier layer, a second semiconductor film, and a third semiconductor film containing a noble (rare) gas element are formed on a first semiconductor film having a crystalline structure. Gettering is performed and a metallic element contained in the first semiconductor film passes through the barrier layer and the second semiconductor film by a heat treatment process, and moves to the third semiconductor film. The second semiconductor film and the third semiconductor film are then removed, with the barrier layer used as an etching stopper.
摘要翻译：目的是减少高温（等于或高于600℃）的热处理工艺步骤，达到较低的温度（等于或小于600℃）的工艺，并简化工艺步骤并增加在制造半导体器件的方法中的吞吐量。通过本发明，在具有结晶结构的第一半导体膜上形成有阻挡层，第二半导体膜和含有贵重（稀有）气体元素的第三半导体膜。进行吸气，并且包含在第一半导体膜中的金属元素通过热处理工艺通过阻挡层和第二半导体膜，并移动到第三半导体膜。然后去除第二半导体膜和第三半导体膜，其中阻挡层用作蚀刻停止层。

19. 发明授权

US07141822B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07141822B2
公开(公告)日：2006-11-28
申请号：US10066542
申请日：2002-02-05
申请人： Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Shunpei Yamazaki , Hideaki Kuwabara
发明人： Osamu Nakamura , Masayuki Kajiwara , Junichi Koezuka , Shunpei Yamazaki , Hideaki Kuwabara
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L21/02532 , H01L21/02672 , H01L21/02675 , H01L27/1277 , H01L27/1296 , H01L29/66757 , H01L29/78621 , Y10S257/913
摘要： The TFT electric characteristic is ready to be influenced by the channel region in the neighborhood of an interface between a semiconductor and a gate insulating film. The present invention provides TFTs reduced in electric characteristic deviations and a method for manufacturing the same. The invention forms a region or layer containing an inactive element, or rear gas element, in the channel region. As shown in FIG. 1, a rear gas element is contained at least in an upper layer of the channel region.
摘要翻译： TFT电气特性准备好受到半导体和栅极绝缘膜之间的界面附近的沟道区的影响。本发明提供了减少电特性偏差的TFT及其制造方法。本发明在通道区域中形成含有非活性元件或后气体元件的区域或层。如图所示。如图1所示，后气体元件至少包含在通道区域的上层中。

20. 发明授权

US07033871B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07033871B2
公开(公告)日：2006-04-25
申请号：US11061780
申请日：2005-02-22
申请人： Osamu Nakamura , Shunpei Yamazaki , Koji Dairiki , Masayuki Kajiwara , Junichi Koezuka , Satoshi Murakami
发明人： Osamu Nakamura , Shunpei Yamazaki , Koji Dairiki , Masayuki Kajiwara , Junichi Koezuka , Satoshi Murakami
IPC分类号： H01L21/00
CPC分类号： H01L27/12 , H01L21/02532 , H01L21/02672 , H01L21/02675 , H01L21/3226 , H01L27/1277 , H01L29/66757 , H01L29/78621 , H01L29/78624 , H01L29/78633 , H01L29/78645 , H01L29/78675
摘要： According to the present invention, an impurity region, to which a rare gas element (also called a rare gas) and one kind or a plurality of kinds of elements selected from the group consisting of H, H2, O, O2, and P are added, are formed in a semiconductor film having a crystalline structure, using a mask, and gettering for segregating a metal element contained in the semiconductor film to the impurity region by heat treatment. Thereafter, pattering is conducted using the mask, whereby a semiconductor layer made of the semiconductor film having a crystalline structure is formed.
摘要翻译：根据本发明，将稀有气体元素（也称为稀有气体）和选自H，H 2 O 2的一种或多种元素的杂质区域，，O，O 2 +和P添加时，使用掩模形成在具有晶体结构的半导体膜中，并且通过使用掩模将包含在半导体膜中的金属元素分离到杂质区域的吸杂热处理。此后，使用掩模进行图案化，由此形成由具有晶体结构的半导体膜制成的半导体层。

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