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    • 16. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME
    • 薄膜晶体管阵列及其制造方法
    • US20100127961A1
    • 2010-05-27
    • US12537702
    • 2009-08-07
    • CHUL HUHKi-Hun JeongJae-Ho ChoiYang-Ho JungJin-Seuk KimSang-Hun LeeGwan-Soo KimSung-Hoon Yang
    • CHUL HUHKi-Hun JeongJae-Ho ChoiYang-Ho JungJin-Seuk KimSang-Hun LeeGwan-Soo KimSung-Hoon Yang
    • G09G3/36
    • G02F1/136227G02F2001/134345G02F2001/136222
    • A thin film transistor array panel including a substrate, gate lines formed on the substrate and extending in a first direction, data lines formed on the substrate and extending in a second direction, wherein the data lines cross and are insulated from the gate lines, and thin film transistors each with a control terminal, an input terminal, and an output terminal. The control and input terminals of the thin film transistor are connected to the gate and data lines. A barrier rib is formed on the gate lines, the data lines, and the thin film transistors. The barrier rib has the same pattern as the gate lines, the data lines, and the thin film transistors. Color filters fill regions demarcated by the barrier rib. Pixel electrodes are formed on the color filters. The output terminal of the thin film transistor has an opening, and a portion of the barrier rib formed on the output terminal has an output opening. The barrier rib output terminal portion has the same pattern as the output terminal. With the thin film transistor array panel, a barrier rib for forming contact holes is formed through exposing a positive photosensitive organic layer formed on a passivation layer to light from the backside of a substrate by using drain electrodes with openings as a light blocking film.
    • 一种薄膜晶体管阵列面板,包括基板,形成在基板上并沿第一方向延伸的栅极线,形成在基板上并沿第二方向延伸的数据线,其中数据线交叉并与栅极线绝缘,以及 薄膜晶体管分别具有控制端子,输入端子和输出端子。 薄膜晶体管的控制和输入端子连接到栅极和数据线。 在栅极线,数据线和薄膜晶体管上形成障壁。 阻挡肋具有与栅极线,数据线和薄膜晶体管相同的图案。 彩色滤光片填充由障壁划分的区域。 像素电极形成在滤色器上。 薄膜晶体管的输出端子具有开口,并且形成在输出端子上的阻挡肋的一部分具有输出开口。 隔壁输出端子部分具有与输出端子相同的图案。 利用薄膜晶体管阵列面板,通过使用具有开口的漏极作为遮光膜,形成用于形成接触孔的阻挡肋,其通过将形成在钝化层上的正性光敏有机层暴露于来自衬底背面的光而形成。
    • 20. 发明授权
    • Thin film transistor array panel for a liquid crystal display
    • 用于液晶显示器的薄膜晶体管阵列面板
    • US06900854B1
    • 2005-05-31
    • US10626617
    • 2003-07-25
    • Dong-Gyu KimJun-Ho SongJong-Woong ChangJae-Ho ChoiByoung-Sun NaYoung-Bae ParkSung-Wook Huh
    • Dong-Gyu KimJun-Ho SongJong-Woong ChangJae-Ho ChoiByoung-Sun NaYoung-Bae ParkSung-Wook Huh
    • G02F1/13G02F1/1343G02F1/1362H01L21/77H01L21/84H01L29/10H01L29/12
    • G02F1/134336G02F1/1362G02F1/136286G02F2001/13606H01L27/124H01L27/1288H01L29/12
    • A gate wire including a gate line extending in the horizontal direction, and a gate electrode is formed on an insulating substrate. A gate insulating layer is formed on the gate wire and covers the same. A semiconductor pattern is formed on the gate insulating layer 30, and formed on the semiconductor pattern are a data wire having a date line in the vertical direction, a source electrode, a drain electrode separated from the source electrode opposite the source electrode with respect to the gate electrode, and an align pattern located on both sides of the data line. A passivation layer is formed on the data wire and the align pattern, and has contact holes exposing the drain electrode and an opening exposing the substrate between the data line and the align pattern. Here, the align pattern adjacent to the data line is exposed through the opening, and the semiconductor pattern and the gate insulating layer are under-cut. A pixel electrode connected to the drain electrode through the contact hole is formed on the passivation layer. Here, the opening is located between the data line and the pixel electrode. In this structure, misalignment occurring in the manufacturing process of a thin film transistor panel for a liquid crystal display is minimized, and stitch defects are prevented by uniformity forming a coupling capacitance between the data line and the pixel electrode. Shorts between the data line and the pixel electrode are prevented by forming the opening between the data line and the pixel electrode.
    • 包括在水平方向延伸的栅极线的栅极线和在绝缘基板上形成栅电极。 栅极绝缘层形成在栅极导线上并覆盖其上。 在栅极绝缘层30上形成半导体图案,在半导体图案上形成有在垂直方向上具有日期线的数据线,源电极,与源电极相对的源电极分离的漏电极相对于 栅极电极和位于数据线两侧的对准图案。 在数据线和对准图案上形成钝化层,并且具有暴露漏电极的接触孔和在数据线和对准图案之间暴露衬底的开口。 这里,与数据线相邻的对准图案通过开口露出,并且半导体图案和栅极绝缘层被切割。 通过接触孔连接到漏电极的像素电极形成在钝化层上。 这里,开口位于数据线和像素电极之间。 在这种结构中,在用于液晶显示器的薄膜晶体管面板的制造过程中发生的偏移被最小化,并且通过在数据线和像素电极之间形成耦合电容的均匀性来防止缝合缺陷。 通过在数据线和像素电极之间形成开口来防止数据线与像素电极之间的短路。