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11. 发明申请

US20050233539A1 Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate 有权
标题翻译：一种在碳化硅半导体衬底中制造具有沟槽的半导体器件的方法
公开(公告)号：US20050233539A1
公开(公告)日：2005-10-20
申请号：US11105587
申请日：2005-04-14
申请人： Yuuichi Takeuchi , Rajesh Malhan , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Yuuichi Takeuchi , Rajesh Malhan , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： C30B23/02 , H01L21/04 , H01L21/306 , H01L21/337 , H01L21/76 , H01L29/04 , H01L29/24 , H01L29/78 , H01L29/808
CPC分类号： H01L29/045 , H01L29/66068 , H01L29/7828 , H01L29/8083
摘要： A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.
摘要翻译：一种制造碳化硅半导体器件的方法包括以下步骤：在半导体衬底的上表面上形成沟槽掩模; 形成沟槽，使得形成具有等于或大于2并且具有等于或大于80度的沟槽倾斜角的纵横比的沟槽; 并且以这样的方式去除损伤部分，即在形成沟槽的步骤中形成在半导体衬底的沟槽的内表面上的损伤部分在氢气气氛中在等于或等于更高的温度的减压下被蚀刻和去除比1600℃

12. 发明授权

US06870189B1 Pinch-off type vertical junction field effect transistor and method of manufacturing the same 失效
标题翻译：夹断型垂直结场效应晶体管及其制造方法
公开(公告)号：US06870189B1
公开(公告)日：2005-03-22
申请号：US10168265
申请日：2000-09-11
申请人： Shin Harada , Kenichi Hirotsu , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Shin Harada , Kenichi Hirotsu , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L21/337 , H01L29/24 , H01L29/772 , H01L29/808 , H01L31/0312 , H01L29/80 , H01L31/112
CPC分类号： H01L29/0843 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/66901 , H01L29/66909 , H01L29/7722 , H01L29/808 , H01L29/8083
摘要： A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conductivity type provided on a surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type that adjoins the source region, a confining region (5) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region (3) of the first conductivity type provided on a reverse face, and a drift region (4) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain. A concentration of an impurity of the first conductivity type in the drift region and the channel region is lower than a concentration of an impurity of the first conductivity type in the source region and the drain region and a concentration of an impurity of the second conductivity type in the confining region.
摘要翻译：提供了一种结型场效应晶体管（JFET），其具有能够以低损耗工作并且几乎没有变化的高电压电阻，高电流切换操作。该JFET设置有设置在半导体衬底的表面上的第二导电类型的栅极区域（2），第一导电类型的源极区域（1），第一导电类型的沟道区域（10）源极区域，邻接栅极区域并限制沟道区域的第二导电类型的约束区域（5），设置在反面上的第一导电类型的漏极区域（3）和漂移区域（4）的第一导电类型，其连续地位于从通道到漏极的衬底的厚度方向上。漂移区域和沟道区域中的第一导电类型的杂质的浓度低于源极区域和漏极区域中的第一导电类型的杂质浓度和第二导电类型的杂质浓度在限制区域。

13. 发明授权

US06660084B1 Sic single crystal and method for growing the same 有权
标题翻译： Sic单晶和生长方法相同
公开(公告)号：US06660084B1
公开(公告)日：2003-12-09
申请号：US10069503
申请日：2002-02-27
申请人： Hiromu Shiomi , Tsunenobu Kimoto , Hiroyuki Matsunami
发明人： Hiromu Shiomi , Tsunenobu Kimoto , Hiroyuki Matsunami
IPC分类号： C30B2502
CPC分类号： C30B23/00 , C30B23/02 , C30B29/36
摘要： A method of growing a 4H-poly type SiC single crystal 40, characterized in that the 4H-poly type SiC single crystal 40 is grown on a seed crystal 30 comprised of an SiC single crystal where a {03-38} plane 30u or a plane which is inclined at off angle &agr;, within about 10°, with respect to the {03-38} plane, is exposed.
摘要翻译：一种生长4H-多晶型SiC单晶40的方法，其特征在于，4H-多晶型SiC单晶40在由SiC单晶构成的晶种30上生长，其中{03-38}面30u或相对于{03-38}平面倾斜偏角α在约10°内的平面被暴露。

14. 发明申请

US20070186858A1 Susceptor 审中-公开
标题翻译：受害者
公开(公告)号：US20070186858A1
公开(公告)日：2007-08-16
申请号：US10594562
申请日：2005-03-28
申请人： Tunenobu Kimoto , Hiroyuki Matsunami , Hirokazu Fujiwara
发明人： Tunenobu Kimoto , Hiroyuki Matsunami , Hirokazu Fujiwara
IPC分类号： C23C16/00
CPC分类号： H01L21/68785 , C23C16/4588 , C30B25/12 , C30B31/14 , H01L21/67103 , H01L21/68757 , H01L21/68771
摘要： A susceptor used in semiconductor epitaxial growth that can simultaneously obtain a plurality of epitaxial films high in uniformity. The susceptor includes a barrel type susceptor having a plurality of surfaces on an outer side of each of which a plurality of substrates can be freely disposed, and a member that has the barrel type susceptor disposed inside thereof and surfaces each of which is oppositely disposed tilting in the same direction as each of the surfaces of the barrel type susceptor. Alternatively, a susceptor includes a barrel type susceptor having a plurality of surfaces on an inner side of each of which a plurality of substrates can be freely disposed, and a member that has the barrel type susceptor disposed at the peripheral portion thereof and surfaces each of which is oppositely disposed tilting in the same direction as each of the surfaces of the barrel type susceptor.
摘要翻译：用于半导体外延生长的感受体可以同时获得高均匀性的多个外延膜。所述基座包括：筒状基座，其外侧上具有多个可自由布置的基板的多个表面;以及具有设置在其内部的所述筒状基座的构件，其表面各倾斜相对设置在与桶形基座的每个表面相同的方向上。或者，基座包括：筒型基座，其内侧具有多个表面，每个表面可以自由地设置多个基板;以及构件，其具有设置在其周边部分的圆筒型基座，其相对地设置在与筒型基座的每个表面相同的方向上倾斜。

15. 发明授权

US07113047B2 Clock generator and its control method 失效
标题翻译：时钟发生器及其控制方法
公开(公告)号：US07113047B2
公开(公告)日：2006-09-26
申请号：US10968005
申请日：2004-10-20
申请人： Hiroyuki Matsunami
发明人： Hiroyuki Matsunami
IPC分类号： H03L7/08
CPC分类号： H03L7/18
摘要： To present a clock generator capable of spreading the spectrum of oscillation frequency by simple control in a small additional circuit, and its control method. A phase locked loop circuit is provided from a frequency phase comparator 11, an output clock signal PO is outputted from a voltage control oscillator (VCO) 14 by way of a charge pump circuit (CP) 12 and a loop filter (LF) 13, and is returned to the frequency phase comparator 11 by way of a frequency divider (DIV) 15. Detecting the phase difference of reference clock signal R and divided clock signal D, and locking the oscillation frequency of the output clock signal PO to specified frequency, a modulation signal M is outputted from a modulation pulse generator 1 regardless of phase locked control of phase locked loop circuit, and is superposed on phase comparison signal P, and thereby the oscillation frequency of output clock signal PO is modulated. An output clock signal PO having a predetermined spectrum spread characteristic can be obtained.
摘要翻译：提出能够通过在小额外电路中简单控制来扩展振荡频率频谱的时钟发生器及其控制方法。从频率相位比较器11提供锁相环电路，通过电荷泵电路（CP）12和环路滤波器（LF）13从压控振荡器（VCO）14输出输出时钟信号PO，并通过分频器（DIV）15返回到频率相位比较器11。检测参考时钟信号R和分频时钟信号D的相位差，并将输出时钟信号PO的振荡频率锁定到指定频率，调制信号M从调制脉冲发生器1输出，不管锁相控制并且叠加在相位比较信号P上，从而调制输出时钟信号PO的振荡频率。可以获得具有预定频谱扩展特性的输出时钟信号PO。

16. 发明授权

US07071675B2 Band distribution inspecting device and band distribution inspecting method 失效
标题翻译：频带分布检测装置和频带分布检测方法
公开(公告)号：US07071675B2
公开(公告)日：2006-07-04
申请号：US10792810
申请日：2004-03-05
申请人： Yasukazu Ono , Koji Okada , Hiroyuki Matsunami
发明人： Yasukazu Ono , Koji Okada , Hiroyuki Matsunami
IPC分类号： G01R23/00 , G01R13/00
CPC分类号： G01R31/2824 , G01R19/0007
摘要： An object of this invention is to provide a band distribution inspecting device and band distribution inspecting method capable of carrying out inspection on whether or not a scattered oscillation signal oscillated containing a frequency variation from the fundamental frequency with the fundamental frequency as a reference point has a band distribution rapidly, with a simple way and at a cheap price. A scattered oscillation signal SSS inputted to a band distribution detecting section 22 is outputted as a predetermined band pass signal SBP through a band pass filter 17 having a predetermined pass band of a predetermined narrow-band width Δf within a band distribution. This signal is converted to a root-mean-square value by a smoother 19, smoothed by a capacitor C1 and transferred to a general purpose inspecting device 21 as a DC signal SAV. The DC signal SAV is compared with a predetermined voltage value VX by a comparator 25 and its comparison result is judged by a judging section 25 and then, an inspection result is outputted as a judging signal J. As a result, an edge frequency in the band distribution of the scattered oscillation signal SSS and disturbance of frequency variation within/out of the band and dullness in waveform and the like can be inspected for.
摘要翻译：本发明的目的是提供一种能够对以基频为基准的包含来自基频的频率变化的振荡信号是否具有振荡的频带分布检查装置和频带分布检查方法进行检查乐队分布迅速，以简单的方式和便宜的价格。输入到频带分布检测部分22的散射振荡信号SSS作为预定的带通信号SBP通过具有预定窄带宽度Deltaf的预定通带的带通滤波器17输出。该信号通过平滑器19转换成均方根值，由电容器C 1平滑，并作为直流信号SAV传送到通用检测装置21。通过比较器25将DC信号SAV与预定的电压值VX进行比较，并且判断部25判断其比较结果，然后作为判断信号J输出检查结果。结果，边缘频率可以检查散射振荡信号SSS的频带分布和波段内/频带内的频率变化的干扰以及波形等中的钝度。

17. 发明申请

US20120212194A1 REFERENCE VOLTAGE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：参考电压电路和半导体集成电路
公开(公告)号：US20120212194A1
公开(公告)日：2012-08-23
申请号：US13316522
申请日：2011-12-11
申请人： Suguru TACHIBANA , Hiroyuki Matsunami , Yukinobu Tanida
发明人： Suguru TACHIBANA , Hiroyuki Matsunami , Yukinobu Tanida
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A reference voltage circuit includes a first amplifier, a first load device and a first PN junction device, second and third load devices and a second PN junction device, an offset voltage reduction circuit, a coupling node potential takeout circuit, and an area adjustment circuit. The offset voltage reduction circuit is configured to reduce an offset voltage between the first and second input terminals at the first amplifier, and the coupling node potential takeout circuit is configured to take out potentials of the first and second coupling nodes. The area adjustment circuit is configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.
摘要翻译：参考电压电路包括第一放大器，第一负载装置和第一PN结装置，第二和第三负载装置和第二PN结装置，偏移电压降低电路，耦合节点势能取出电路和区域调整电路。偏移电压降低电路被配置为减少第一放大器处的第一和第二输入端之间的偏移电压，并且耦合节点电势取出电路被配置为取出第一和第二耦合节点的电位。区域调整电路被配置为根据由耦合节点电势取出电路取出的第一和第二耦合节点的电位来调整第二PN结装置的面积。

18. 发明授权

US07671388B2 Lateral junction field effect transistor and method of manufacturing the same 有权
公开(公告)号：US07671388B2
公开(公告)日：2010-03-02
申请号：US12552212
申请日：2009-09-01
申请人： Kazuhiro Fujikawa , Shin Harada , Kenichi Hirotsu , Satoshi Hatsukawa , Takashi Hoshino , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Kazuhiro Fujikawa , Shin Harada , Kenichi Hirotsu , Satoshi Hatsukawa , Takashi Hoshino , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L29/78
CPC分类号： H01L29/0634 , H01L29/1058 , H01L29/1066 , H01L29/42316 , H01L29/66893 , H01L29/808
摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

19. 发明授权

US07420232B2 Lateral junction field effect transistor and method of manufacturing the same 有权
标题翻译：横向场效应晶体管及其制造方法
公开(公告)号：US07420232B2
公开(公告)日：2008-09-02
申请号：US11402701
申请日：2006-04-11
申请人： Kazuhiro Fujikawa , Shin Harada , Kenichi Hirotsu , Satoshi Hatsukawa , Takashi Hoshino , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Kazuhiro Fujikawa , Shin Harada , Kenichi Hirotsu , Satoshi Hatsukawa , Takashi Hoshino , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L29/0634 , H01L29/1058 , H01L29/1066 , H01L29/42316 , H01L29/66893 , H01L29/808
摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
摘要翻译：横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及具有与第一栅极电极层相同的电位。因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

20. 发明授权

US07241694B2 Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate 有权
标题翻译：一种在碳化硅半导体衬底中制造具有沟槽的半导体器件的方法
公开(公告)号：US07241694B2
公开(公告)日：2007-07-10
申请号：US11105587
申请日：2005-04-14
申请人： Yuuichi Takeuchi , Rajesh Kumar Malhan , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Yuuichi Takeuchi , Rajesh Kumar Malhan , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L21/18 , H01L21/302 , H01L21/308
CPC分类号： H01L29/045 , H01L29/66068 , H01L29/7828 , H01L29/8083
摘要： A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.
摘要翻译：一种制造碳化硅半导体器件的方法包括以下步骤：在半导体衬底的上表面上形成沟槽掩模; 形成沟槽，使得形成具有等于或大于2并且具有等于或大于80度的沟槽倾斜角的纵横比的沟槽; 并且以这样的方式去除损伤部分，即在形成沟槽的步骤中形成在半导体衬底的沟槽的内表面上的损伤部分在氢气气氛中在等于或等于更高的温度的减压下被蚀刻和去除比1600℃

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