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11. 发明申请

US20100003800A1 BIPOLAR TRANSISTOR WITH SILICIDED SUB-COLLECTOR 有权
标题翻译：双极晶体管，带有硅分集电极
公开(公告)号：US20100003800A1
公开(公告)日：2010-01-07
申请号：US12557557
申请日：2009-09-11
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L21/331
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided.
摘要翻译：本发明的实施例提供一种制造半导体器件的方法。该方法包括在掺杂半导体材料层中限定子集电极区; 在所述掺杂半导体材料层的顶部上形成有源区，电介质区和到达区，所述电介质区将所述有源区与所述覆盖区分离; 并且将通过区域和子集电极区域的一部分硅化以形成部分硅化物的导电路径。还提供了由此制成的半导体器件。

12. 发明授权

US07550361B2 Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels 失效
标题翻译：用于混合光学和电子束平版印刷制造水平的共同对准的沟槽结构和方法
公开(公告)号：US07550361B2
公开(公告)日：2009-06-23
申请号：US11618957
申请日：2007-01-02
申请人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
发明人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
IPC分类号： H01L21/76
CPC分类号： H01L21/76283 , B82Y10/00 , B82Y40/00 , G03F7/7045 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01J37/3174 , H01L21/3081 , H01L21/823481 , H01L21/84 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.
摘要翻译：一种用于将集成电路芯片的制造级别的第一组特征对准到形成在衬底中的电子束对准目标并使用电子束光刻形成第一组特征并用于对准第二组特征的方法将集成电路芯片的制造水平设置到形成在基板中的光学对准目标，并且使用光刻法形成第二组特征，所述光学对准目标本身与电子束对准目标对准。还有一种形成电子束对准靶的方法和结构。

13. 发明申请

US20080164494A1 BIPOLAR TRANSISTOR WITH SILICIDED SUB-COLLECTOR 有权
标题翻译：双极晶体管，带有硅分集电极
公开(公告)号：US20080164494A1
公开(公告)日：2008-07-10
申请号：US11620242
申请日：2007-01-05
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L29/737 , H01L29/73 , H01L21/04
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.
摘要翻译：本发明的实施例提供了一种在有源区域中包括集电极的半导体器件; 第一和第二子集电极，所述第一子集电极是与所述集电极相邻的重掺杂半导体材料，所述第二子集电极是靠近所述第一子集电极的硅化副集电极; 以及与所述第二子集电器接触的硅化物到达通道，其中所述第一和第二子集电极和所述硅化物到达通道为所述集电器从所述有源区域收集的电荷提供连续的导电路径。本发明的实施例还提供了制造该方法的方法。

14. 发明申请

US20070222066A1 STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS 有权
标题翻译：形成电沉积联系的结构和方法
公开(公告)号：US20070222066A1
公开(公告)日：2007-09-27
申请号：US11308433
申请日：2006-03-24
申请人： Cyril Cabral , Hariklia Deligianni , Randolph Knarr , Sandra Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe Vereecken
发明人： Cyril Cabral , Hariklia Deligianni , Randolph Knarr , Sandra Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe Vereecken
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.
摘要翻译：一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

15. 发明申请

US20070218641A1 FULLY SILICIDED EXTRINSIC BASE TRANSISTOR 失效
标题翻译：完全硅酸超级基极晶体管
公开(公告)号：US20070218641A1
公开(公告)日：2007-09-20
申请号：US11308259
申请日：2006-03-14
申请人： David Ahlgren , Guy Cohen , Christian Lavoie , Francois Pagette , Anna Topol
发明人： David Ahlgren , Guy Cohen , Christian Lavoie , Francois Pagette , Anna Topol
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/1004 , H01L29/1608 , H01L29/66242 , H01L29/66287 , H01L29/732 , H01L29/7378
摘要： A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermined amount of time, the silicidation substantially stopping at the intrinsic base. The system and method further includes forming an emitter which is physically insulated from the extrinsic base and the collector, and which is in physical contact with the intrinsic base.
摘要翻译：一种系统和方法包括在收集器上形成固有碱基。该系统和方法还包括通过在预定温度下的自限硅化工艺在本征基底上形成完全硅化的外在碱，并且预定量的时间，硅化物在本征碱基本上停止。该系统和方法还包括形成与外部基极和集电器物理绝缘的发射极，并与内部基极物理接触。

16. 发明授权

US08089157B2 Contact metallurgy structure 有权
标题翻译：接触冶金结构
公开(公告)号：US08089157B2
公开(公告)日：2012-01-03
申请号：US12967633
申请日：2010-12-14
申请人： Cyril Cabral, Jr. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
发明人： Cyril Cabral, Jr. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed.
摘要翻译：一种接触式冶金结构，包括在衬底上具有通孔的图案化介电层; 位于通孔底部的钴和/或镍的硅化物层; 包含位于硅化物层顶部的通孔中的Ti的接触层; 位于接触层的通孔和顶部的扩散层; 提供通孔中的金属填充层以及制造方法。金属填充层包括选自铜，钌，铑铂，钯，铱，铼，钨，金，银和锇中的至少一种及其合金。当金属填充层包含铑时，不需要扩散层。任选地，可以使用用于金属填充层的种子层。

17. 发明申请

US20100081232A1 LAYER TRANSFER PROCESS AND FUNCTIONALLY ENHANCED INTEGRATED CIRCUITS PRODUCED THEREBY 有权
标题翻译：层级传输过程和功能强化的集成电路
公开(公告)号：US20100081232A1
公开(公告)日：2010-04-01
申请号：US12544226
申请日：2009-08-20
申请人： Bruce K. Furman , Sampath Purushothaman , Muthumanickam Sankarapandian , Anna Topol
发明人： Bruce K. Furman , Sampath Purushothaman , Muthumanickam Sankarapandian , Anna Topol
IPC分类号： H01L21/50 , H01L21/768
CPC分类号： H01L21/768 , H01L21/2007 , H01L21/84 , H01L23/3735 , H01L27/0688 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.
摘要翻译：提供了一种用于半导体部件的结构，其具有通过其它有源，无源和互连部件夹在两侧的器件层。使用晶片级层传输过程来创建具有附加功能增强的平面（2D）IC结构。

18. 发明授权

US07679164B2 Bipolar transistor with silicided sub-collector 有权
标题翻译：双极晶体管，带硅化子集电极
公开(公告)号：US07679164B2
公开(公告)日：2010-03-16
申请号：US11620242
申请日：2007-01-05
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L27/102
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.
摘要翻译：本发明的实施例提供了一种在有源区域中包括集电极的半导体器件; 第一和第二子集电极，所述第一子集电极是与所述集电极相邻的重掺杂半导体材料，所述第二子集电极是靠近所述第一子集电极的硅化副集电极; 以及与所述第二子集电器接触的硅化物到达通道，其中所述第一和第二子集电极和所述硅化物到达通道为所述集电器从所述有源区域收集的电荷提供连续的导电路径。本发明的实施例还提供了制造该方法的方法。

19. 发明申请

US20080157404A1 TRENCH STRUCTURE AND METHOD FOR CO-ALIGNMENT OF MIXED OPTICAL AND ELECTRON BEAM LITHOGRAPHIC FABRICATION LEVELS 失效
标题翻译：混合光学和电子束光刻制造水平对准的TRENCH结构和方法
公开(公告)号：US20080157404A1
公开(公告)日：2008-07-03
申请号：US11618957
申请日：2007-01-02
申请人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
发明人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
IPC分类号： H01L23/544 , G03F7/20 , H01L21/76
CPC分类号： H01L21/76283 , B82Y10/00 , B82Y40/00 , G03F7/7045 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01J37/3174 , H01L21/3081 , H01L21/823481 , H01L21/84 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.
摘要翻译：一种用于将集成电路芯片的制造级别的第一组特征对准到形成在衬底中的电子束对准目标并使用电子束光刻形成第一组特征并用于对准第二组特征的方法将集成电路芯片的制造水平设置到形成在基板中的光学对准目标，并且使用光刻法形成第二组特征，所述光学对准目标本身与电子束对准目标对准。还有一种形成电子束对准靶的方法和结构。

20. 发明申请

US20070281439A1 Techniques for Layer Transfer Processing 审中-公开
标题翻译：层传输处理技术
公开(公告)号：US20070281439A1
公开(公告)日：2007-12-06
申请号：US11840389
申请日：2007-08-17
申请人： Stephen Bedell , Keith Fogel , Bruce Furman , Sampath Purushothaman , Devendra Sadana , Anna Topol
发明人： Stephen Bedell , Keith Fogel , Bruce Furman , Sampath Purushothaman , Devendra Sadana , Anna Topol
IPC分类号： H01L21/30 , H01L21/00
CPC分类号： H01L21/76259 , Y10T428/249961
摘要： Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a thee dimensional integrated structure is provided.
摘要翻译：提供了制造半导体器件的技术。一方面，提供了层转移结构。层转移结构包括具有调谐孔隙度的多孔区域的载体衬底以及限定分离平面的注入物质的组合。另一方面，提供了一种形成层转移结构的方法。另一方面，提供了一种形成一维一体结构的方法。

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