专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5355020A Semiconductor device having a multi-layer metal contact 失效
标题翻译：具有多层金属接触的半导体器件
公开(公告)号：US5355020A
公开(公告)日：1994-10-11
申请号：US910894
申请日：1992-07-08
申请人： Sang-in Lee , Jeong-in Hong , Jong-ho Park
发明人： Sang-in Lee , Jeong-in Hong , Jong-ho Park
IPC分类号： H01L23/52 , H01L21/027 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/0276 , H01L21/28512 , H01L21/76855 , H01L21/76858 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L23/485 , H01L23/53223 , H01L23/53271 , H01L2924/0002
摘要： A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via) and a first conductive layer formed on the insulating layer which completely fills the opening. The first conductive layer does not produce any Si precipitates in a subsequent heat-treating step for filling the opening with the first conductive layer material. The semiconductor device may further include a second conductive layer having a planarized surface on the first conductive layer. This improves subsequent photolithography. An anti-reflective layer may be formed on the second conductive layer for preventing an unwanted reflection during a photo lithography process. The semiconductor device preferably includes a diffusion barrier layer under the first conductive layer and on the semiconductor substrate, on the insulating layer, and on the inner surface of the opening which prevents a reaction between the first conductive layer and the semiconductor substrate or the insulating layer. A method for forming the wiring layer is also disclosed. Providing a semiconductor device with the wiring layer reduces the leakage current by preventing an Al spiking. Since the first conductive layer undergoes a heat-treatment step at a temperature below the melting point, while flowing into the opening and completely filling it with the first conductive layer material, no void is formed in the opening. Good semiconductor device reliability is ensured in spite of the contact hole being less than 1 .mu.m in size and having an aspect ratio greater than 1.0.
摘要翻译：公开了具有新型接触结构的半导体器件的布线层。半导体器件包括半导体衬底，具有开口（接触孔或通孔）的绝缘层和形成在绝缘层上的完全填充开口的第一导电层。在随后的用第一导电层材料填充开口的热处理步骤中，第一导电层不产生任何Si沉淀物。半导体器件还可以包括在第一导电层上具有平坦化表面的第二导电层。这改善了随后的光刻。可以在第二导电层上形成抗反射层，以防止在光刻工艺期间不期望的反射。半导体器件优选地包括在第一导电层下方，半导体衬底上的绝缘层上的扩散阻挡层，以及防止第一导电层与半导体衬底或绝缘层之间的反应的开口内表面。还公开了一种用于形成布线层的方法。提供具有布线层的半导体器件通过防止Al尖峰来减少泄漏电流。由于第一导电层在低于熔点的温度下经历热处理步骤，同时流入开口并用第一导电层材料完全填充，因此在开口中不形成空隙。尽管接触孔的尺寸小于1μm，纵横比大于1.0，仍然保证良好的半导体器件的可靠性。

12. 发明授权

US5229325A Method for forming metal wirings of semiconductor device 失效
标题翻译：用于形成半导体器件的金属布线的方法
公开(公告)号：US5229325A
公开(公告)日：1993-07-20
申请号：US758603
申请日：1991-09-12
申请人： Jong-Ho Park , Deok-Min Lee , Sang-in Lee
发明人： Jong-Ho Park , Deok-Min Lee , Sang-in Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/7684
摘要： A method for forming metal wires of a semiconductor device includes the steps of first forming about half of the total metal wires, the wires being arranged at regular intervals, forming sidewall spacers made of insulating materials on the metal wires using an etchback method, and forming the rest of the total wires at spaces between the wires of the first half, again using an etchback process. This results in a wire structure in which a gap between adjacent metal wires is about 0.1 microns in width.
摘要翻译：用于形成半导体器件的金属线的方法包括以下步骤：首先形成总金属线的大约一半，电线以规则的间隔布置，使用回蚀法在金属线上形成由绝缘材料制成的侧壁隔离物，以及形成在上半部分的电线之间的间隔处的总线的其余部分再次使用回蚀工艺。这导致相邻金属线之间的间隙宽度为约0.1微米的线结构。

13. 发明授权

US06270572B1 Method for manufacturing thin film using atomic layer deposition 有权
标题翻译：使用原子层沉积制造薄膜的方法
公开(公告)号：US06270572B1
公开(公告)日：2001-08-07
申请号：US09371709
申请日：1999-08-09
申请人： Yeong-kwan Kim , Sang-in Lee , Chang-soo Park , Sang-min Lee
发明人： Yeong-kwan Kim , Sang-in Lee , Chang-soo Park , Sang-min Lee
IPC分类号： C30B2502
CPC分类号： H05B33/04 , C23C16/44 , C23C16/45527 , C23C16/45561 , H01L21/02381 , H01L21/0254 , H01L21/0262 , H01L21/02631 , H01L21/31604 , H01L21/31691
摘要： A thin film manufacturing method is provided. The method includes the step of chemically adsorbing a first reactant on a substrate by injecting the first reactant into a chamber in which the substrate is loaded. Physisorbed first reactant on the chemically adsorbed first reactant is removed by purging or pumping the chamber. After the first reactant is densely chemically adsorbed on the substrate by re-injecting the first reactant into the chamber, the physisorbed first reactant on the dense chemisorbed first reactant is removed by purging or pumping the chamber. A second reactant is chemically adsorbed onto the surface of the substrate by injecting the second reactant into the chamber. Physisorbed second reactant on the chemisorbed first reactant and the second reactant is removed by purging or pumping the chamber. A solid thin film is formed by chemical exchange through densely adsorbing the second reactant onto the substrate by re-injecting the second reactant into the chamber. According to the present invention, it is possible to obtain a precise stoichiometric thin film having a high film density, since the first reactant and the second reactant are densely adsorbed and the impurities are substantially removed by pumping or purging
摘要翻译：提供薄膜制造方法。该方法包括通过将第一反应物注入到其中负载衬底的室中来在基底上化学吸附第一反应物的步骤。化学吸附的第一反应物上的物理吸附的第一反应物通过清洗或泵送室来除去。在第一反应物通过将第一反应物重新注入室中密集地化学吸附在基材上之后，通过清洗或泵送室来去除致密化学吸附的第一反应物上的物理吸附的第一反应物。通过将第二反应物注入到室中，将第二反应物化学吸附到基底的表面上。化学吸附的第一反应物和第二反应物上的物理吸附的第二反应物通过清洗或泵送室来除去。通过将第二反应物重新注入到室中，将第二反应物密集地吸附到基底上，通过化学交换形成固体薄膜。根据本发明，可以获得具有高膜密度的精确化学计量薄膜，因为第一反应物和第二反应物被密集吸附并且通过泵送或清除基本上除去杂质

14. 发明授权

US06197683B1 Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact of semiconductor device using the same 有权
标题翻译：通过化学气相沉积形成金属氮化物膜的方法和使用其形成半导体器件的金属接触的方法
公开(公告)号：US06197683B1
公开(公告)日：2001-03-06
申请号：US09156724
申请日：1998-09-18
申请人： Sang-bom Kang , Chang-soo Park , Yun-sook Chae , Sang-in Lee
发明人： Sang-bom Kang , Chang-soo Park , Yun-sook Chae , Sang-in Lee
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , C23C16/34 , C23C16/45553 , H01L21/28562 , H01L21/28568 , H01L21/76804 , H01L28/91
摘要： A method of forming a metal nitride film using chemical vapor deposition (CVD), and a method of forming a metal contact of a semiconductor device using the same, are provided. The method of forming a metal nitride film using chemical vapor deposition (CVD) in which a metal source and a nitrogen source are used as a precursor, includes the steps of inserting a semiconductor substrate into a deposition chamber, flowing the metal source into the deposition chamber, removing the metal source remaining in the deposition chamber by cutting off the inflow of the metal source and flowing a purge gas into the deposition chamber, cutting off the purge gas and flowing the nitrogen source into the deposition chamber to react with the metal source adsorbed on the semiconductor substrate, and removing the nitrogen source remaining in the deposition chamber by cutting off the inflow of the nitrogen source and flowing the purge gas into the deposition chamber. Accordingly, the metal nitride film has low resistivity and a low content of Cl even with excellent step coverage, and it can be formed at a temperature of 500° C. or lower. Also, a deposition speed, approximately 20 Å/cycle, is suitable for mass production.
摘要翻译：提供了使用化学气相沉积（CVD）形成金属氮化物膜的方法，以及使用其形成使用其的半导体器件的金属接触的方法。使用其中使用金属源和氮源作为前体的化学气相沉积（CVD）形成金属氮化物膜的方法包括以下步骤：将半导体衬底插入淀积室中，使金属源流入沉积物通过切断金属源的流入并将净化气体流入沉积室，去除沉积室中残留的金属源，切断净化气体并使氮源流入沉积室以与金属源反应吸附在半导体衬底上，并且通过切断氮源的流入并将净化气体流入沉积室来除去留在沉积室中的氮源。因此，即使具有优异的阶梯覆盖，金属氮化物膜也具有低电阻率和低的Cl含量，并且可以在500℃或更低的温度下形成。此外，沉积速度约为每秒的一个循环，适合批量生产。

15. 发明授权

US6140671A Semiconductor memory device having capacitive storage therefor 失效
标题翻译：具有电容存储的半导体存储器件
公开(公告)号：US6140671A
公开(公告)日：2000-10-31
申请号：US157401
申请日：1998-09-21
申请人： Sang-in Lee
发明人： Sang-in Lee
IPC分类号： H01L27/04 , H01L21/02 , H01L21/285 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/04 , H01L27/105 , H01L29/16 , H01L29/92
CPC分类号： H01L27/10852 , H01L28/55 , H01L28/60 , H01L21/28568 , Y10S148/148
摘要： A capacitor in a semiconductor device having a dielectric film formed of high dielectric material and a manufacturing method therefor are provided. The capacitor consists of electrodes including a dielectric film and an amorphous SiC layer. Thus, the diffusion of oxygen atoms through a grain boundary into an underlayer and the formation of an oxide layer on the surface of the SiC layer can both be prevented, providing for a highly reliable capacitor electrode and an equivalent oxide thickness which is no thicker than required.
摘要翻译：提供了具有由高介电材料形成的电介质膜的半导体器件中的电容器及其制造方法。电容器由包括电介质膜和非晶SiC层的电极组成。因此，可以防止氧原子通过晶界扩散到底层中，并且可以防止在SiC层的表面上形成氧化物层，从而提供高可靠性的电容器电极和等于不比厚度大的氧化物厚度需要。

16. 发明授权

US6001660A Methods of forming integrated circuit capacitors using metal reflow techniques 失效
标题翻译：使用金属回流技术形成集成电路电容器的方法
公开(公告)号：US6001660A
公开(公告)日：1999-12-14
申请号：US969672
申请日：1997-11-13
申请人： Young-soh Park , Sang-in Lee , Cheol-seong Hwang , Doo-sup Hwang , Hag-Ju Cho
发明人： Young-soh Park , Sang-in Lee , Cheol-seong Hwang , Doo-sup Hwang , Hag-Ju Cho
IPC分类号： C23C14/14 , C23C14/58 , H01L21/02 , H01L21/28 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01G7/06
CPC分类号： H01L28/60 , H01L21/76882
摘要： Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer on a face of a semiconductor substrate and then patterning the electrically insulating layer to define a contact hole therein. A barrier metal layer is then formed in at least a portion of the contact hole. A lower electrode metal layer is then formed on the barrier metal layer and then planarized by reflowing the lower electrode metal layer at a temperature greater than about 650.degree. C. in a nitrogen gas ambient, to define a lower capacitor electrode. A layer of material having a high dielectric constant is then formed on the lower capacitor electrode. An upper capacitor electrode is then formed on the dielectric layer, opposite the lower capacitor electrode. The dielectric layer may comprise Ba(Sr, Ti)O.sub.3, Pb(Zr, Ti)O.sub.3, Ta.sub.2 O.sub.5, SiO.sub.2, SiN.sub.3, SrTiO.sub.3, PZT, SrBi.sub.2 Ta.sub.2 O.sub.9, (Pb, La)(Zr, Ti)O.sub.3 and Bi.sub.4 Ti.sub.3 O.sub.12. According to one embodiment of the present invention, the step of patterning the electrically insulating layer comprises patterning the electrically insulating layer to define a contact hole therein that exposes the face of the semiconductor substrate. The step of forming a barrier metal layer also preferably comprises depositing a conformal barrier metal layer on sidewalls of the contact hole and on the exposed face of the substrate. The barrier metal layer may be selected from the group consisting of TiN, CoSi, TaSiN, TiSiN, TaSi, TiSi, Ta and TaN.
摘要翻译：形成集成电路电容器的方法包括以下步骤：在半导体衬底的表面上形成电绝缘层，然后对电绝缘层进行构图以在其中限定接触孔。然后在接触孔的至少一部分中形成阻挡金属层。然后在阻挡金属层上形成下电极金属层，然后通过在氮气环境中在大于约650℃的温度下回流下电极金属层来平坦化，以限定较低的电容器电极。然后在下部电容器电极上形成具有高介电常数的材料层。然后在电介质层上形成上电容器电极，与下电容器电极相对。介电层可以包括Ba（Sr，Ti）O3，Pb（Zr，Ti）O3，Ta2O5，SiO2，SiN3，SrTiO3，PZT，SrBi2Ta2O9，（Pb，La）（Zr，Ti）O3和Bi4Ti3O12。根据本发明的一个实施例，图案化电绝缘层的步骤包括图案化电绝缘层以限定其中露出半导体衬底的表面的接触孔。形成阻挡金属层的步骤还优选包括在接触孔的侧壁上和基底的暴露面上沉积保形阻挡金属层。阻挡金属层可以选自TiN，CoSi，TaSiN，TiSiN，TaSi，TiSi，Ta和TaN。

17. 发明授权

US5970309A Method of manufacturing a capacitor and a capacitor electrode in semiconductor device 失效
标题翻译：在半导体器件中制造电容器和电容器电极的方法
公开(公告)号：US5970309A
公开(公告)日：1999-10-19
申请号：US950887
申请日：1997-10-15
申请人： Jung-min Ha , Byung-lyul Park , Dae-hong Ko , Sang-in Lee
发明人： Jung-min Ha , Byung-lyul Park , Dae-hong Ko , Sang-in Lee
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1085 , H01L28/60 , H01L28/82
摘要： A method of manufacturing a semiconductor capacitor electrode by growing a metal compound layer over polysilicon storage nodes. The metal compound layer readily growing on the polysilicon storage nodes, but not on portions of an insulating layer between adjacent polysilicon storage nodes.
摘要翻译：一种通过在多晶硅储存节点上生长金属化合物层来制造半导体电容器电极的方法。金属化合物层容易生长在多晶硅存储节点上，而不是在相邻的多晶硅存储节点之间的绝缘层的部分上生长。

18. 发明授权

US5939787A Semiconductor device having a multi-layer contact structure 失效
标题翻译：具有多层接触结构的半导体器件
公开(公告)号：US5939787A
公开(公告)日：1999-08-17
申请号：US929419
申请日：1997-09-15
申请人： Sang-in Lee
发明人： Sang-in Lee
IPC分类号： H01L21/28 , C23C14/06 , C23C14/24 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L29/43
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L21/76882 , H01L23/532 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor device and manufacturing method thereof having a diffusion barrier layer formed on a semiconductor wafer, whose surface region is provided with a silylation layer, wherein the silylation layer is formed on the diffusion barrier layer which is formed on the semiconductor wafer, by a plasma process using silicon hydride or by a reactive sputtering method using SiH.sub.4. When the metal layer is formed on the silylation layer, the wettability between the diffusion barrier layer and the metal is enhanced and large grains are formed, thereby increasing the step coverage for the contact hole of the metal layer or for the via hole. Additionally, when heat treatment is performed after the metal layer is formed on the silylation layer, the reflow characteristic of the metal layer becomes good, to thereby facilitate the filling of the contact hole or the via hole easy. When the wiring layer is thus formed, the metal wiring having good reliability can be obtained and the subsequent process is rendered unnecessary.
摘要翻译：一种半导体器件及其制造方法，其具有形成在半导体晶片上的扩散阻挡层，其表面区域设置有甲硅烷基化层，其中所述甲硅烷基层通过等离子体形成在形成在半导体晶片上的扩散阻挡层上使用硅氢化物或通过使用SiH 4的反应溅射法进行。当在甲硅烷基层上形成金属层时，扩散阻挡层和金属之间的润湿性增强，并且形成大的晶粒，从而增加金属层或通孔的接触孔的阶梯覆盖。此外，当在甲硅烷基层上形成金属层之后进行热处理时，金属层的回流特性变好，从而易于使接触孔或通孔的填充。当这样形成布线层时，可以获得具有良好可靠性的金属布线，并且不需要随后的处理。

19. 发明授权

US5851917A Method for manufacturing a multi-layer wiring structure of a semiconductor device 失效
标题翻译：半导体装置的多层布线结构的制造方法
公开(公告)号：US5851917A
公开(公告)日：1998-12-22
申请号：US625114
申请日：1996-04-01
申请人： Sang-in Lee
发明人： Sang-in Lee
IPC分类号： H01L21/285 , H01L21/441 , H01L21/48 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532 , H01L21/28
CPC分类号： H01L21/76838 , H01L21/76843 , H01L21/76856 , H01L21/76862 , H01L21/76876 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： A wiring structure of semiconductor device and a method for manufacturing the same which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole or a via hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plug is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface thereof the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for the semiconductor device of the next generation.
摘要翻译：半导体器件的布线结构及其制造方法，其填充低于一半微米的接触孔。绝缘层形成在半导体衬底上，并且在绝缘层中形成接触孔或通孔。在绝缘层上，通过CVD法沉积第一金属，以形成填充接触孔的CVD金属层或CVD金属塞。然后，将如此获得的CVD金属层或CVD金属插塞在低于第一金属的熔点的高温下在真空中进行热处理，从而平坦化其CVD金属层的表面。通过溅射法在CVD金属层或CVD金属插塞上沉积第二种金属，从而形成溅射金属层。通过CVD法将接触孔填充第一金属，然后通过溅射法沉积可靠的溅射金属层。布线层可用于下一代的半导体器件。

20. 发明授权

US5723384A Method for manufacturing a capacitor in a semiconductor device using selective tungsten nitride thin film 失效
标题翻译：在使用选择性氮化钨薄膜的半导体器件中制造电容器的方法
公开(公告)号：US5723384A
公开(公告)日：1998-03-03
申请号：US713944
申请日：1996-09-13
申请人： Byung-lyul Park , Jung-min Ha , Dae-hong Ko , Sang-in Lee
发明人： Byung-lyul Park , Jung-min Ha , Dae-hong Ko , Sang-in Lee
IPC分类号： H01L27/04 , H01L21/02 , H01L21/31 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： There is provided a method for manufacturing a capacitor in a semiconductor device including the steps of forming first and second insulating layers with a first contact hole through to a semiconductor substrate, patterning a first conductive layer to form a pedestal portion of a lower electrode, using a patterned third insulating layer selectively forming an upper portion of the lower electrode from a tungsten nitride thin film, and forming an undercut beneath the pedestal portion by wet-etching the second insulating layer.
摘要翻译：提供了一种用于制造半导体器件中的电容器的方法，包括以下步骤：将具有第一接触孔的第一绝缘层和第二绝缘层形成至半导体衬底，使第一导电层图案化以形成下电极的基座部分，使用图案化的第三绝缘层，从氮化钨薄膜选择性地形成下部电极的上部，并通过湿式蚀刻第二绝缘层，在底座部分下方形成底切。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式