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11. 发明授权

US07799645B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07799645B2
公开(公告)日：2010-09-21
申请号：US12232148
申请日：2008-09-11
申请人： Jung-Dal Choi , Young-Woo Park , Jin-Taek Park , Chung-Il Hyun
发明人： Jung-Dal Choi , Young-Woo Park , Jin-Taek Park , Chung-Il Hyun
IPC分类号： H01L21/8236
CPC分类号： H01L21/8236 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An embodiment of a semiconductor device includes a substrate including a cell region and a peripheral region; a cell gate pattern on the cell region; and a peripheral gate pattern on the peripheral region, wherein a first cell insulation layer, a second cell insulation layer, and a third cell insulation layer may be between the substrate and the cell gate pattern, a first peripheral insulation layer, a second peripheral insulation layer, and a third peripheral insulation layer may be between the substrate and the peripheral gate pattern, and the second cell insulation layer and the third cell insulation layer include the same material as the respective second peripheral insulation layer and third peripheral insulation layer.
摘要翻译：半导体器件的实施例包括：包括单元区域和周边区域的衬底; 单元格区域上的单元格栅图案; 以及周边区域上的外围栅极图案，其中第一电池绝缘层，第二电池绝缘层和第三电池绝缘层可以在衬底和电池栅极图案之间，第一外围绝缘层，第二外围绝缘层层和第三外围绝缘层可以在基板和外围栅极图案之间，并且第二电池绝缘层和第三电池绝缘层包括与相应的第二外围绝缘层和第三外围绝缘层相同的材料。

12. 发明授权

US07872295B2 Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same 有权
标题翻译：制造具有STI的闪速存储器单元和外围电路的方法，以及具有该闪速存储器单元的闪速存储器单元和外围电路
公开(公告)号：US07872295B2
公开(公告)日：2011-01-18
申请号：US12367988
申请日：2009-02-09
申请人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
发明人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
IPC分类号： H01L29/94
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11546 , H01L27/11592 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.
摘要翻译：集成电路包括闪存单元，以及包括低压晶体管（LVT）和高压晶体管（HVT））的外围电路。集成电路包括包含SiON，SiN或其它高k材料的隧道势垒层。隧道势垒层可以包括HVT的栅极电介质的一部分。隧道势垒层可以构成HVT的整个栅电介质。相应的隧道势垒层可以形成在浅沟槽隔离（STI）之间或之间。因此，可以提高驱动器芯片IC的制造效率。

13. 发明申请

US20090072298A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090072298A1
公开(公告)日：2009-03-19
申请号：US12232148
申请日：2008-09-11
申请人： Jung-Dal Choi , Young-Woo Park , Jin-Taek Park , Chung-il Hyun
发明人： Jung-Dal Choi , Young-Woo Park , Jin-Taek Park , Chung-il Hyun
IPC分类号： H01L27/115 , H01L21/8246
CPC分类号： H01L21/8236 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An embodiment of a semiconductor device includes a substrate including a cell region and a peripheral region; a cell gate pattern on the cell region; and a peripheral gate pattern on the peripheral region, wherein a first cell insulation layer, a second cell insulation layer, and a third cell insulation layer may be between the substrate and the cell gate pattern, a first peripheral insulation layer, a second peripheral insulation layer, and a third peripheral insulation layer may be between the substrate and the peripheral gate pattern, and the second cell insulation layer and the third cell insulation layer include the same material as the respective second peripheral insulation layer and third peripheral insulation layer.
摘要翻译：半导体器件的实施例包括：包括单元区域和外围区域的衬底; 单元格区域上的单元格栅图案; 以及周边区域上的外围栅极图案，其中第一电池绝缘层，第二电池绝缘层和第三电池绝缘层可以在衬底和电池栅极图案之间，第一外围绝缘层，第二外围绝缘层层和第三外围绝缘层可以在基板和外围栅极图案之间，并且第二电池绝缘层和第三电池绝缘层包括与相应的第二外围绝缘层和第三外围绝缘层相同的材料。

14. 发明授权

US08188532B2 Semiconductor device having a gate contact structure capable of reducing interfacial resistance 有权
标题翻译：具有能够降低界面电阻的栅极接触结构的半导体器件
公开(公告)号：US08188532B2
公开(公告)日：2012-05-29
申请号：US12856295
申请日：2010-08-13
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的插塞使多晶硅层通过开口接触。

15. 发明申请

US20110031559A1 SEMICONDUCTOR DEVICES IN WHICH A CELL GATE PATTERN AND A RESISTOR PATTERN ARE FORMED OF A SAME MATERIAL AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：细胞栅格图案和电阻图案的半导体器件形成相同的材料及其形成方法
公开(公告)号：US20110031559A1
公开(公告)日：2011-02-10
申请号：US12905517
申请日：2010-10-15
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L28/20
摘要： A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, farming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.
摘要翻译：通过提供包括单元区域，外围电路区域和电阻器区域的半导体衬底形成半导体器件，在半导体衬底上形成器件隔离层以限定有源区，形成第一绝缘层和多晶硅在外围电路区域的有源区上形成图案，在单元区域的有源区上形成第二绝缘层，电荷存储层和第三绝缘层，在半导体衬底上耕作导电层，并且使导电层以在单元区域的第三绝缘层上形成导电图案，分别形成外围电路区域的有源区域的多晶硅图案和电阻器区域的半导体衬底。

16. 发明授权

US07816245B2 Method of forming semiconductor devices in which a cell gate pattern and a resistor pattern are formed of a same material 有权
标题翻译：形成其中单元栅极图案和电阻器图案由相同材料形成的半导体器件的方法
公开(公告)号：US07816245B2
公开(公告)日：2010-10-19
申请号：US11648992
申请日：2007-01-03
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/3205
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L28/20
摘要： A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, forming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.
摘要翻译：通过提供包括单元区域，外围电路区域和电阻器区域的半导体衬底形成半导体器件，在半导体衬底上形成器件隔离层以限定有源区，形成第一绝缘层和多晶硅在外围电路区域的有源区上形成图案，在单元区域的有源区上形成第二绝缘层，电荷存储层和第三绝缘层，在半导体衬底上形成导电层，并且使导电层以在单元区域的第三绝缘层上形成导电图案，分别形成外围电路区域的有源区域的多晶硅图案和电阻器区域的半导体衬底。

17. 发明授权

US07645644B2 Data line layout in semiconductor memory device and method of forming the same 有权
标题翻译：半导体存储器件中的数据线布局及其形成方法
公开(公告)号：US07645644B2
公开(公告)日：2010-01-12
申请号：US12113994
申请日：2008-05-02
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , H01L27/105 , H01L27/1052
摘要： In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n
摘要翻译：在一个方面，提供了一种半导体器件，其包括数据块，该数据块包括M个并行且顺序排列的数字线，编号为{0,1,2。。。 n，n + 1，。。。，m-1，m}，其中M，n和m是正整数，并且其中n

18. 发明授权

US07605430B2 Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same 失效
标题翻译：具有鳍状有源区的非易失性存储器件及其制造方法
公开(公告)号：US07605430B2
公开(公告)日：2009-10-20
申请号：US11474699
申请日：2006-06-23
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.
摘要翻译：非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。翅片形有源区形成在器件隔离层的各部分之间。侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。侧壁保护层可以使用器件隔离层形成。或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

19. 发明申请

US20070104011A1 Cell array of semiconductor memory device and a method of forming the same 有权
标题翻译：半导体存储器件的单元阵列及其形成方法
公开(公告)号：US20070104011A1
公开(公告)日：2007-05-10
申请号：US11507511
申请日：2006-08-22
申请人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
发明人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.
摘要翻译：电池阵列包括半导体衬底，其包括包括第一区域，第二区域和过渡区域的有源区域，第二区域与第一区域分离过渡区域，其中第二区域的顶表面处于与第一区域的顶表面不同的水平。单元阵列还包括跨越第一区域的多个字线。单元阵列还包括在有源区上交叉的选择线，其中选择线的至少一部分位于过渡区上方。

20. 发明申请

US20060289944A1 Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same 失效
公开(公告)号：US20060289944A1
公开(公告)日：2006-12-28
申请号：US11474699
申请日：2006-06-23
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.

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