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    • 11. 发明授权
    • Piezoactuator drive detection device and electronic device
    • 压电驱动器检测装置和电子装置
    • US07439650B2
    • 2008-10-21
    • US11476057
    • 2006-06-28
    • Akihiro Sawada
    • Akihiro Sawada
    • H01L41/08
    • G04C3/12G04C17/0058H02N2/0025H02N2/004H02N2/026H02N2/062H02N2/103H02N2/142
    • To provide a drive detection means for a piezoelectric actuator that can detect an amount driven without requiring adding an encoder or other component while also preventing increasing the load. A rotor is disposed eccentrically to the axis of rotation to change the pressure applied from the rotor to a contact part as the rotor is driven. When the pressure changes, the amplitude of the detection signal output from the detection electrode 18 of the piezoelectric element changes in conjunction with rotor rotation, and how much the rotor has been driven can be detected by detecting the amplitude change. Size and thickness can therefore be reduced because providing an encoder, switch, or other component is unnecessary, and current consumption can also be reduced.
    • 提供一种用于压电致动器的驱动检测装置,该驱动器检测装置可以在不需要增加编码器或其它部件的同时也能够检测驱动量,同时也防止增加负载。 当转子被驱动时,转子偏心地设置在旋转轴上,以将从转子施加的压力改变为接触部分。 当压力变化时,从压电元件的检测电极18输出的检测信号的振幅与转子旋转一起变化,并且可以通过检测振幅变化来检测转子多少。 因此,由于不需要提供编码器,开关或其他部件,因此可以减小尺寸和厚度,并且还可以减少电流消耗。
    • 13. 发明申请
    • Pll frequency synthesizer
    • Pll频率合成器
    • US20070096834A1
    • 2007-05-03
    • US10559867
    • 2005-05-12
    • Akihiro Sawada
    • Akihiro Sawada
    • H03L7/00
    • H03L7/0898H03L7/093H03L7/18
    • A PLL frequency synthesizer is provided with a linearization circuit 6 which receives an oscillation frequency control signal VT from a loop filter LF. The linearization circuit 6 outputs a charge pump current control signal CPCONT, depending on a potential level of the oscillation frequency control signal VT. The larger the value of the charge pump current control signal CPCONT, the higher the potential level. A charge pump CP receives the charge pump current control signal CPCONT, and causes a current corresponding to the value to flow in or out. Therefore, with a simple circuit structure, loop gain characteristics of the PLL frequency synthesizer can be regulated to be constant. Therefore, even when a variable capacitance element incorporated in a voltage control oscillator has nonlinear characteristics with respect to the potential of the input oscillation frequency control signal, the loop gain characteristics of the PLL frequency synthesizer having the voltage control oscillator can be regulated to be constant.
    • PLL频率合成器具有从环路滤波器LF接收振荡频率控制信号V SUB的线性化电路6。 线性化电路6根据振荡频率控制信号V SUBT的电位电平输出电荷泵电流控制信号CP CONT 。 电荷泵电流控制信号CP 的值越大,电位电平越高。 电荷泵CP接收电荷泵电流控制信号CP ,并使与该值对应的电流流入或流出。 因此,通过简单的电路结构,可以将PLL频率合成器的环路增益特性调节为恒定。 因此,即使在电压控制振荡器中结合的可变电容元件相对于输入振荡频率控制信号的电位具有非线性特性,也可以将具有电压控制振荡器的PLL频率合成器的环路增益特性调节为恒定 。
    • 14. 发明授权
    • Electronic timepiece with controlled date display updating
    • 电子钟表控制日期显示更新
    • US06912181B2
    • 2005-06-28
    • US10371749
    • 2003-02-21
    • Akihiko MaruyamaAkihiro Sawada
    • Akihiko MaruyamaAkihiro Sawada
    • G04C9/00G04C10/04G04C17/00G04G19/12G04C3/00G04B1/00G04C23/00
    • G04C17/0066G04G19/12
    • An electronic timepiece without system failure at the time of transfer from the power-saving mode to the display mode is provided. A power-saving control circuit 400 controls drive of a date dial displaying a date when updating a date display, which has been stopped in a power-saving mode, to a current date at the time of transfer from the power-saving mode to the display mode. The power-saving control circuit 400 outputs a date dial drive inhibiting signal, which prohibits drive of the date dial 75, to a date-updating control circuit 300, if a voltage VDD of a power source unit B is less than or equal to a low threshold voltage V1. It outputs a date dial deceleration driving signal, which drives a date dial 75 with a predetermined speed slower than a normal update speed when transferring to the display mode, to a date-updating control circuit 300, if a source voltage VDD is equal to or less than a high threshold voltage V2.
    • 提供了在从省电模式转移到显示模式时没有系统故障的电子钟表。 省电控制电路400控制显示将在节电模式中已经停止的日期显示更新的日期的日期拨盘的驱动变换为从省电模式传送到当前日期的当前日期 显示模式。 如果电源单元B的电压VDD小于或等于1,则省电控制电路400输出禁止日期拨盘75的驱动的日期拨盘驱动禁止信号到日期更新控制电路300 低阈值电压V1。 如果源电压VDD等于或等于或者等于或者等于或者等于或者等于或者等于或者等于或者等于或者等于或者等于或者等于或者等于 小于高阈值电压V2。
    • 18. 发明申请
    • PHASE LOCKED LOOP CIRCUIT AND WIRELESS COMMUNICATION SYSTEM
    • 相位锁定环路和无线通信系统
    • US20090102570A1
    • 2009-04-23
    • US12194836
    • 2008-08-20
    • Seiichiro YoshidaAkihiro Sawada
    • Seiichiro YoshidaAkihiro Sawada
    • H03L7/099
    • H03L7/099H03L7/087H03L7/091H03L7/10H03L2207/06
    • In a PLL circuit including a VCO having a plurality of oscillation frequency bands, a TDC circuit calculates a phase difference between a predetermined reference signal from a fixed frequency divider and a PLL frequency-divided signal from a variable frequency divider on a rising edge of the reference signal and then calculates a phase difference between the reference signal and the PLL frequency-divided signal on the next rising edge of the reference signal in the same manner. From information on the two calculated phase differences, the TDC circuit detects the amount of time by which the phase of the PLL frequency-divided signal leads or lags with respect to that of the reference signal in one cycle of the reference signal, thereby detecting which of the signals, the reference signal or the PLL frequency-divided signal, has a higher frequency and which has a lower frequency. Therefore, for each oscillation frequency band, the frequency comparison is completed in one cycle of the reference signal, allowing an oscillation frequency band selection circuit to detect an optimum oscillation frequency band corresponding to a predetermined PLL output frequency in a short time.
    • 在包括具有多个振荡频带的VCO的PLL电路中,TDC电路计算来自固定分频器的预定参考信号与来自可变分频器的PLL分频信号之间的相位差, 参考信号,然后以相同的方式在参考信号的下一个上升沿计算参考信号和PLL分频信号之间的相位差。 根据两个计算出的相位差的信息,TDC电路检测PLL分频信号的相位在参考信号的一个周期中相对于参考信号的相位导致或滞后的时间量,从而检测哪个 的信号,参考信号或PLL分频信号具有较高的频率,频率较低。 因此,对于每个振荡频带,在参考信号的一个周期内完成频率比较,允许振荡频带选择电路在短时间内检测对应于预定PLL输出频率的最佳振荡频带。
    • 19. 发明授权
    • PLL frequency synthesizer
    • PLL频率合成器
    • US07327195B2
    • 2008-02-05
    • US10559867
    • 2005-05-12
    • Akihiro Sawada
    • Akihiro Sawada
    • H03L7/00
    • H03L7/0898H03L7/093H03L7/18
    • A PLL frequency synthesizer is provided with a linearization circuit 6 which receives an oscillation frequency control signal VT from a loop filter LF. The linearization circuit 6 outputs a charge pump current control signal CPCONT, depending on a potential level of the oscillation frequency control signal VT. The larger the value of the charge pump current control signal CPCONT, the higher the potential level. A charge pump CP receives the charge pump current control signal CPCONT, and causes a current corresponding to the value to flow in or out. Therefore, with a simple circuit structure, loop gain characteristics of the PLL frequency synthesizer can be regulated to be constant. Therefore, even when a variable capacitance element incorporated in a voltage control oscillator has nonlinear characteristics with respect to the potential of the input oscillation frequency control signal, the loop gain characteristics of the PLL frequency synthesizer having the voltage control oscillator can be regulated to be constant.
    • PLL频率合成器具有从环路滤波器LF接收振荡频率控制信号V SUB的线性化电路6。 线性化电路6根据振荡频率控制信号V SUBT的电位电平输出电荷泵电流控制信号CP CONT 。 电荷泵电流控制信号CP 的值越大,电位电平越高。 电荷泵CP接收电荷泵电流控制信号CP ,并使与该值对应的电流流入或流出。 因此,通过简单的电路结构,可以将PLL频率合成器的环路增益特性调节为恒定。 因此,即使在电压控制振荡器中结合的可变电容元件相对于输入振荡频率控制信号的电位具有非线性特性,也可以将具有电压控制振荡器的PLL频率合成器的环路增益特性调节为恒定 。