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11. 发明授权

US5818110A Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same 失效
标题翻译：具有交叉能力的集成电路芯片布线结构及其制造方法
公开(公告)号：US5818110A
公开(公告)日：1998-10-06
申请号：US755077
申请日：1996-11-22
申请人： John Edward Cronin
发明人： John Edward Cronin
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5221 , H01L21/76877 , H01L23/5329 , H01L2924/0002 , Y10S257/923
摘要： An integrated circuit chip wiring structure having crossover and contact capability without an interlock via layer and a method of making the wiring structure all disclosed. The method utilizes a multi-damascene approach, using the standard damascene processing steps to wire the first, then metallization layer, then providing the second, thick metallization layer with first regions for metal wire. A conformal coating is deposited, filling the second regions but not the first regions. When an etch is performed, the layers underlying the second regions are exposed but not those underlying the second regions. Therefore, it is possible to selectively expose the metal lines in the first layer so that electrical connection is made with the metal wire of the second layer in the exposed areas. Electrical isolation is maintained in the narrower, second regions of metal wire.
摘要翻译：具有不具有互锁通路层的交叉接触能力的集成电路芯片布线结构和全部公开了布线结构的方法。该方法使用多镶嵌方法，使用标准镶嵌处理步骤来对第一层，然后金属化层进行接线，然后为第二厚金属化层提供金属线的第一区域。沉积保形涂层，填充第二区域而不是第一区域。当进行蚀刻时，第二区域下面的层被暴露，但不暴露第二区域的层。因此，可以选择性地暴露第一层中的金属线，使得在暴露区域中与第二层的金属线进行电连接。在金属丝的较窄的第二区域中保持电隔离。

12. 发明授权

US5719438A Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging 失效
公开(公告)号：US5719438A
公开(公告)日：1998-02-17
申请号：US469090
申请日：1995-06-06
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Wayne John Howell , James Marc Leas , David Jacob Perlman
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Wayne John Howell , James Marc Leas , David Jacob Perlman
IPC分类号： H01L21/98 , H01L23/498 , H01L25/065 , H01L25/18 , H01L23/02 , H01L23/04
CPC分类号： H01L25/50 , H01L23/49827 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/49107 , H01L2224/49109 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16152 , H01L2924/16195 , H01L2924/30107
摘要： A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

13. 发明授权

US5661330A Fabrication, testing and repair of multichip semiconductor structures having connect assemblies with fuses 失效
标题翻译：具有熔断器连接组件的多芯片半导体结构的制造，测试和修复
公开(公告)号：US5661330A
公开(公告)日：1997-08-26
申请号：US404005
申请日：1995-03-14
申请人： Bruno Roberto Aimi , John Edward Cronin , Andre Conrad Forcier , James Marc Leas , Patricia McGuinnes Marmillion , Anthony Michael Palagonia , Bernadette Ann Pierson , Dennis Arthur Schmidt
发明人： Bruno Roberto Aimi , John Edward Cronin , Andre Conrad Forcier , James Marc Leas , Patricia McGuinnes Marmillion , Anthony Michael Palagonia , Bernadette Ann Pierson , Dennis Arthur Schmidt
IPC分类号： H01L21/82 , G01R31/28 , H01L21/66 , H01L23/52 , H01L25/065 , H01L29/00
CPC分类号： G01R31/2863 , G01R31/2884 , H01L22/22 , H01L25/0657 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2924/0002
摘要： A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity. The second conductive level includes islands of strap conductors that electrically interconnect the isolated conductors of the first conductive level. The first conductive level and a second conductive level are constructed of different conductive material which may be separately etched so that the second conductive level may be removed without affecting this first conductive level.
摘要翻译：本发明提供一种具有连接组件的多芯片半导体结构和制造方法，其具有促进烧结应力和结构电气测试的熔断器。该结构包括具有到其边缘表面的标准传输线的多芯片叠层。至少一些到边缘表面的导线具有电连接到其上的熔丝，使得在老化应力期间应当产生过大的电流源/漏，相应的保险丝将断开。还公开了导电结构，其有助于在老化应力和测试之前在多芯片结构的边缘表面上形成最终的可操作的金属化布线。该导电结构包括第一导电水平和第二导电水平。第一导电电平具有绝缘导体，其端部紧邻设置。第二导电电平包括带状导体岛，其电连接第一导电电平的隔离导体。第一导电水平和第二导电水平由不同的导电材料构成，其可以被单独蚀刻，使得可以去除第二导电水平而不影响该第一导电水平。

14. 发明授权

US5654221A Method for forming semiconductor chip and electronic module with integrated surface interconnects/components 失效
标题翻译：用于形成具有集成表面互连/部件的半导体芯片和电子模块的方法
公开(公告)号：US5654221A
公开(公告)日：1997-08-05
申请号：US419318
申请日：1995-04-10
申请人： John Edward Cronin , Stephen Ellinwood Luce , Steven Howard Voldman
发明人： John Edward Cronin , Stephen Ellinwood Luce , Steven Howard Voldman
IPC分类号： H01L25/00 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/16 , H01L25/18 , H01L21/283 , H01L21/329
CPC分类号： H01L25/50 , H01L23/535 , H01L25/0657 , H01L25/16 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2924/0002 , H01L2924/3011
摘要： A fabrication method and resultant electronic module having one or more surfaces enhanced with interconnects and components. Electronic modules having, for example, resistors and capacitors integral with a side surface thereof are disclosed. Further described are electronic modules with interconnects electrically attaching for example, side to side, or side to end surfaces are described. Moreover, discussion of an electronic module having a Silicon Front Face chip is contained herein. Specific details of the fabrication method, resulting electronic module, and related wafer processing are set forth.
摘要翻译：具有通过互连和部件增强的一个或多个表面的制造方法和结果电子模块。公开了具有例如与其侧表面成一体的电阻器和电容器的电子模块。进一步描述了具有例如彼此电连接的互连件的电子模块，例如，侧向或侧向或端对端的表面。此外，在此包含具有硅正面芯片的电子模块的讨论。阐述了制造方法，所得到的电子模块和相关晶片处理的具体细节。

15. 发明申请

US20140196529A1 SYSTEM AND METHOD FOR SENSING AND MANAGING POTHOLE LOCATION AND POTHOLE CHARACTERISTICS 有权
标题翻译：用于感测和管理孔位置和孔特征的系统和方法
公开(公告)号：US20140196529A1
公开(公告)日：2014-07-17
申请号：US13742928
申请日：2013-01-16
申请人： John Edward Cronin , Benjamin Shields Taylor , William Petrow , Edward Joseph Limoge , Stephen Douglas Garland
发明人： John Edward Cronin , Benjamin Shields Taylor , William Petrow , Edward Joseph Limoge , Stephen Douglas Garland
IPC分类号： E01C23/00
CPC分类号： E01C23/01 , E01C23/06 , G06F17/30997 , G06Q50/26
摘要： The present invention provides a system and method for sensing and managing pothole locations and pothole characteristics. An additional aspect of the present invention is to provide a system that may acquire, fuse, and analyze pothole sensing data from several sources to identify potholes in need of maintenance or repair. Further, the system may be configured to create and distribute recurring reports of pothole repair data for use by roadway officials.
摘要翻译：本发明提供了一种用于感测和管理坑洞位置和坑洞特征的系统和方法。本发明的另一方面是提供一种系统，其可以从多个源获取，熔化和分析井底感测数据，以识别需要维护或修理的坑洞。此外，该系统可以被配置为创建和分发窑坑修复数据的重复报告以供道路官员使用。

16. 发明授权

US06950220B2 Electro-optic displays, and methods for driving same 有权
标题翻译：电光显示器及其驱动方法
公开(公告)号：US06950220B2
公开(公告)日：2005-09-27
申请号：US10249128
申请日：2003-03-18
申请人： Justin Abramson , Karl R. Amundson , Guy M. Danner , Gregg M. Duthaler , Holly G. Gates , Charles H. Honeyman , Ara N. Knaian , Ian D. Morrison , Steven J. O'Neil , Richard J. Paolini, Jr. , Anthony Edward Pullen , Jianna Wang , Jonathan L. Zalesky , Robert W. Zehner , John Edward Cronin
发明人： Justin Abramson , Karl R. Amundson , Guy M. Danner , Gregg M. Duthaler , Holly G. Gates , Charles H. Honeyman , Ara N. Knaian , Ian D. Morrison , Steven J. O'Neil , Richard J. Paolini, Jr. , Anthony Edward Pullen , Jianna Wang , Jonathan L. Zalesky , Robert W. Zehner , John Edward Cronin
IPC分类号： G02F1/15
CPC分类号： G02F1/15 , G02F1/1521 , G02F2201/42
摘要： The invention relates to electro-optic displays and methods for driving such displays. The invention provides (i) electrochromic displays with solid charge transport layers; (ii) apparatus and methods for improving the contrast and reducing the cost of electrochromic displays; (iii) apparatus and methods for sealing electrochromic displays from the outside environment and preventing ingress of contaminants into such a display; and (iv) methods for adjusting the driving of electro-optic displays to allow for environmental and operating parameters.
摘要翻译：本发明涉及用于驱动这种显示器的电光显示器和方法。本发明提供（i）具有固体电荷传输层的电致变色显示器; （ii）用于改善电色差显示器的对比度和降低成本的装置和方法; （iii）从外部环境密封电致变色显示器并防止污染物进入这种显示器的装置和方法; 以及（iv）用于调节电光显示器的驱动以允许环境和操作参数的方法。

17. 发明授权

US5955818A Machine structures fabricated of multiple microstructure layers 失效
标题翻译：由多个微结构层制造的机器结构
公开(公告)号：US5955818A
公开(公告)日：1999-09-21
申请号：US999871
申请日：1997-11-04
申请人： Claude Louis Bertin , John Edward Cronin
发明人： Claude Louis Bertin , John Edward Cronin
IPC分类号： B81B5/00 , B81B7/00 , B81C1/00 , B81C3/00 , H01H1/00 , H01L21/306 , H01L29/84 , H01L49/00 , H02N1/00 , H01L41/08
CPC分类号： H01H1/0036 , H02N1/004
摘要： Machine structures each comprising a stack of a plurality of micromachine layers laminated together are presented, along with fabrication methods therefore. Each machine structure includes a movable member(s) defined from microstructure of at least one layer of the plurality of micromachine layers comprising the stack. During fabrication, the micromachine layers are separately formed using VLSI techniques and then subsequently laminated together in a selected arrangement in the stack to define the machine structure.
摘要翻译：因此，提供了各自包括层叠在一起的多个微机械层的堆叠的机械结构，以及制造方法。每个机器结构包括由包括该堆叠的多个微机械层的至少一层的微结构限定的可移动构件。在制造期间，使用VLSI技术分开形成微机械层，然后在堆叠中以选定的布置层叠在一起以限定机器结构。

18. 发明授权

US5818748A Chip function separation onto separate stacked chips 失效
标题翻译：芯片功能分离到单独的堆叠芯片上
公开(公告)号：US5818748A
公开(公告)日：1998-10-06
申请号：US560222
申请日：1995-11-21
申请人： Claude Louis Bertin , John Edward Cronin
发明人： Claude Louis Bertin , John Edward Cronin
IPC分类号： G11C5/02 , H01L25/065 , H01L27/02
CPC分类号： H01L27/0207 , G11C5/025 , H01L25/0657 , H01L2224/81899 , H01L2225/06513 , H01L2225/06527
摘要： The high-voltage drivers and decoders of a direct-write EEPROM memory array are separated from the word lines and placed onto separate stacked chips. The separate chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are used to physically and electrically connect the separate chips.
摘要翻译：直写EEPROM存储器阵列的高电压驱动器和解码器与字线分离并放置在单独的堆叠芯片上。单独的芯片是面对面堆叠的，并且力响应自联动微连接器用于物理和电连接分开的芯片。

19. 发明授权

US5804853A Stacked electrical device having regions of electrical isolation and electrical connections on a given stack level 失效
标题翻译：在给定的堆叠级上具有电隔离和电连接区域的堆叠式电气设备
公开(公告)号：US5804853A
公开(公告)日：1998-09-08
申请号：US686881
申请日：1996-07-26
申请人： John Edward Cronin , John Kenneth DeBrosse , Hing Wong
发明人： John Edward Cronin , John Kenneth DeBrosse , Hing Wong
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L2924/0002
摘要： A semiconductor structure having electrical conductors positioned over each other, but electrically isolated from each other, is disclosed. The lower conductor has a recess in its upper surface, and the recess is at least partially filled with an oxide-type material, thereby isolating the lower conductor from the upper conductor. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. Stacked capacitor cells incorporating this structure are also disclosed.
摘要翻译：公开了一种半导体结构，其具有彼此相互定位但彼此电隔离的电导体。下导体在其上表面具有凹槽，并且凹部至少部分地填充有氧化物型材料，从而将下导体与上导体隔离。这些导体通常彼此接触，因为用于制造多个导电元件（例如非常致密的半导体结构）的图案化和蚀刻步骤有些不精确。还公开了结合该结构的堆叠电容器电池。

20. 发明授权

US5781031A Programmable logic array 失效
标题翻译：可编程逻辑阵列
公开(公告)号：US5781031A
公开(公告)日：1998-07-14
申请号：US560250
申请日：1995-11-21
申请人： Claude Louis Bertin , John Edward Cronin
发明人： Claude Louis Bertin , John Edward Cronin
IPC分类号： H01L25/065 , H03K19/177 , H01L23/02
CPC分类号： H03K19/1776 , H01L25/0657 , H03K19/17704 , H03K19/17796 , H01L2224/81899 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06593 , H01L2924/13091
摘要： A programmable logic array (PLA) includes two direct-write EEPROM arrays, and PLA logic circuitry, such as feedback, drivers and input and output circuitry. One EEPROM array acts as an AND array and the other acts as n OR array. The PLA can be used for a memory function or a PLA function. In one aspect, the EEPROM arrays are placed on a first chip and the PLA logic circuitry a second chip. The first and second chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are used to physically and electrically connect the separate chips. The separate chips are fabricated concurrently to reduce turn-around time.
摘要翻译：可编程逻辑阵列（PLA）包括两个直写EEPROM阵列和PLA逻辑电路，如反馈，驱动器和输入和输出电路。一个EEPROM阵列充当AND阵列，另一个作为n OR阵列。 PLA可用于记忆功能或PLA功能。在一个方面，EEPROM阵列放置在第一芯片上，PLA逻辑电路放置在第二芯片上。第一和第二芯片面对面堆叠，并且力响应自联锁微型连接器用于物理和电连接分开的芯片。单独的芯片是同时制造的，以减少周转时间。

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